Mitsubishi Denki Kabushiki Kaisha

Renesas Electronics Corporation

Renesas Technology Corp.

Renesas Lsi Design Corporation

Other

Mitsubishi Electric System Lsi Design Corporation

Atsuo Yamaguchi

Shuzo Fujioka

Kenichi Takahira

Toshiyuki Matsubara

Shigeru Furuta

Takesi Inoue

Kazuhiko Fukushima

Shigenori Miyauchi

Hirokazu Tsuruta

Etsushi Takebayashi

A data processing apparatus is provided, which detects falsification of software to data and rewriting of the data. The data processing apparatus according to an embodiment of the present invention comprises a security unit which has an encryption circuit for decrypting an encrypted signal including secrecy data. The security unit includes a compression circuit which compresses an access signal used in accessing the security unit and outputs the compression result, and a comparison circuit which compares the compression result outputted from the compression circuit with a previously-calculated expectation value of the compression result of the access signal.

Data processing apparatus

A random number generator includes a ring oscillator having an EX-OR gate and four inverters together forming a loop. This loop enters stable state for a start signal having the low level and oscillates for the start signal having the high level. When the start signal has a pulse of a width shorter than the loop's delay time, output nodes responsively, sequentially enter metastable state hovering between the high and low levels. The metastable waveform becomes smaller with time and finally disappears. As metastable state cannot be controlled in longevity, it disappears at any random number node. A counter thus outputs a signal serving as true random number data depending on the longevity of the metastable state. A random number generator miniaturized and having reduced power consumption, and of high performance can thus be implemented.

Random number generator with ring oscillation circuit

To provide a semiconductor device which can perform initialization to a first state of two states of the first state and a second state, and which can generate a signal having a potential corresponding to the initialized first state. The present invention is the semiconductor device which can perform initialization to '0' (a first state) of two states of '0' and &#x201c;1&#x201d; (a second state), and which can generate a signal having a potential corresponding to initialized &#x201c;0&#x201d;. The semiconductor deviceincludes a plurality of flip-flop circuitsthat are connected in parallel and which can hold the two states of &#x201c;0&#x201d; and &#x201c;1&#x201d;; and an AND circuitwhich generates and outputs a signal having a potential corresponding to &#x201c;0&#x201d; when a state held in at least one flip-flop circuitamong the flip-flop circuitsis &#x201c;0&#x201d;. The AND circuit is connected to the flip-flop circuits

Semiconductor device

An encoding/decoding operation portion includes an encoding/decoding operation circuit and an avoiding path for detouring the encoding decoding operation circuit and can select between encoding or decoding input data in the encoding/decoding operation circuit and detouring the encoding/decoding operation circuit to output the input data without change. Only one wire has to be provided from a selector to a key storage portion and an initialization-vector storage portion. With this construction, it is possible to realize an encoding/decoding circuit which can suppress an increase in the number of wires used to transmit a content of key data to the key storage portion and the initialization-vector storage portion and does not cause complication of circuit layout.

Encoding/decoding circuit

An addition and subtraction circuit performs addition and subtraction using a carry-in signal from another operation circuit, and outputs a carry-out signal generated through addition and subtraction to another operation circuit. A right-shift circuit performs right-shift using a shift-in signal from another operation circuit, and outputs a shift-out signal generated through right-shift to another operation circuit. Therefore, even if a data length of operation data is extended, a propagation path for a carry can be shortened, and an operation clock frequency of an encryption circuit can be increased.

Encryption circuit achieving higher operation speed

A power-residue calculating unit includes a K register connected to a first internal bus for once storing an intermediate calculation result to be discarded when a power-residue calculation is executed in accordance with a binary method. Therefore even when data to be discarded appears during the calculation, a write into K register is performed, so that current in a write operation flows thereby improving immunity against Power Analysis.

Residue calculating unit immune to power analysis

A non-contact IC card system capable of improving the data transmission rate and communication range without considerably enlarging the frequency band of a signal to be put to use. An AM-modulated signal ( F) from a reader writer ( ) is received by a resonance circuit ( ) of an IC card ( ), and an IC card driving power source is produced therefrom in a rectifying section ( ). In addition, it is demodulated in an AM demodulating circuit ( ) and decoded in a decoder ( ), thereby presenting reception data ( ). On the other hand, when data ( J) is transmitted from the IC card ( ), a characteristic of a regulator ( ) for stabilizing an operating voltage of the resonance circuit ( ) is altered on the basis of a signal encoded in an encoder ( ) so that the signal is transmitted as an AM-modulated signal ( P) to the reader writer ( ).

Non-contact IC card system and non-contact IC card

A charge pump circuit comprises a plurality of booster stages. Each booster stage has a first node, a second node, a first charge pump and a second charge pump. Both charge pumps operate in a complementary manner, and raise potential of the second node relative to potential of the first node by transferring charge from the first node to the second node. Each charge pump comprises a pumping capacitor, an NMOS transistor and a PMOS transistor. In each charge pump, the NMOS transistor is used for charging the pumping capacitor with charge input through the first node, and the PMOS transistor is used for discharging the pumping capacitor to send charge to the second node.

Charge pump circuit

A PLL circuit is disclosed which can achieve a locked state in a short time. The PLL circuit has a phase comparator, a loop filter and a voltage controlled oscillator. The phase comparator is provided with frequency adjusting (or matching) circuits that are operative to charge the loop filter when it is detected that an oscillation frequency of the voltage controlled oscillator is lower than a frequency of an input signal, so as to increase the oscillation frequency of the voltage controlled oscillator, until it is detected that an oscillation frequency of the voltage controlled oscillator is higher than the frequency of the input signal. Similarly, the loop filter is discharged when it is detected that an oscillation frequency of the voltage controlled oscillator is higher than a frequency of an input signal, so as to decrease the oscillation frequency of the voltage controlled oscillator, until it is detected that an oscillation frequency of the voltage controlled oscillator is lower than the frequency of the input signal. The phase comparator is further provided with phase adjusting (or matching) circuits for adjusting a phase of an output of the voltage controlled oscillator to a phase of the input signal after the oscillator frequency of the voltage controlled oscillator is adjusted to the frequency of the input signal. Thus, a time required to adjust the oscillation frequency of the voltage controlled oscillator can be considerably reduced.

PLL circuit

A batteryless non-contact IC card, using electromagnetic waves as a communication medium, includes an antenna resonance circuit for data transmission and reception; a phase variation detector for detecting a phase variation of a voltage of the antenna resonance circuit due to a received signal, on the basis of an amplitude variation of the received signal; and a demodulator for demodulating data in accordance with the phase variation detected by the phase variation detector.

Non-contact IC card with phase variation detector

A non-contact IC card includes an antenna resonance circuit including two output terminals; and a phase locked loop (PLL) for receiving, as an input signal, a signal representative of a received signal received by the IC card and changing to a negative state, and for producing an output tuned to the input signal, wherein, for phase modulation or demodulation, an output signal for half a period is produced as the output of the PLL and both terminals of an antenna resonance circuit are short-circuited during the half period from a zero crossing point of the input signal.

Growing community of inventors

Itami, Japan

Atsuo Yamaguchi