Renesas Technology Corp.

Mitsubishi Denki Kabushiki Kaisha

Mitsubishi Electric Engineering Company, Limited

Atsuo Mangyo

Akira Yamazaki

Takeshi Fujino

Makoto Hatakenaka

Koji Nii

Masaru Haraguchi

Isamu Hayashi

Manabu Miura

Masashi Matsumura

When to a memory cell arraya read/write operation is performed of the 7-bit data in which parity bits of 3 bits are added to data of 4 bits, an error correction is carried out in concern to each of the 7-bit data. The memory cell array is divided into memory unitstoeach of which has four bits which are arranged along a direction of a word line. On writing the 7-bit data in the memory cell array, bits of the 7-bit data that are different from one another are written as written bit data along the direction of the word line in the memory unitsto, respectively. In the 7-bit data, the written bit data has an interval of four bits. Error correcting circuits performs an error correction of the 7-bit data in each of the 7-bit data.

Memory circuit

A semiconductor integrated circuit device includes test data output nodes arranged in a width of a plurality of bits and an internal data bus, greater in bit width than the test data output nodes, for transferring internal data. A predetermined number of bits of the internal data on the internal data bus are compared with bits of test expected value data equal in bit width to the test data output nodes for each bit. The predetermined number of bits of the internal data are selected in accordance with a test address signal. The bits selected is compared with the respective bits of the test expected valued data. Data indicating respective comparison results are output to the test data output nodes in parallel.

Semiconductor integrated circuit device with test data output nodes for parallel test results output

A test clock signal for determining timing of transferring a signal to an embedded memory, a memory clock signal for determining timing of latching signal/data of the embedded memory, and a latch timing signal for sampling a signal read from the memory are selectively sampled in accordance with a correcting test clock signal by a common flip flop. The phase differences of the latch timing signal, test clock signal and memory clock signal are measured externally. Thus, it is possible to accurately measure timing conditions such as set up/hold time and access time of the embedded synchronous memory.

Semiconductor circuit device capable of accurately testing embedded memory

A semiconductor memory device includes a first data line electrically connected to selected one of a plurality of memory cells in response to activation of a word line, a second data line provided hierarchically with respect to the first data line, a read circuit provided between the first data line and the second data line to drive the second data line to a fixed voltage with a driving power according to a voltage on the first data line at the time of data reading, and a voltage supply control circuit for supplying a predetermined voltage to the second data line in response to a precharge/equalize instruction. The voltage supply control circuit includes a voltage supply stop circuit disconnecting the second data line from the predetermined voltage in a predetermined period except for the time of data reading.

Semiconductor memory device with power consumption reduced in non-data-access

A method for testing a semiconductor memory device according to one embodiment comprises the steps of: checking data in all addresses of the semiconductor memory device for correctness in-units of m&times;n bits: ending if it is determined that data in all the semiconductor memory device; if there is a defective address, comparing each m-bit data constituting the (m&times;n)-bit data corresponding to the defective address with its expected value; and if the comparison result indicates that the m-bit data is erroneous, determining whether the defective semiconductor memory device can be repaired. Due to this step, man hours required for testing a semiconductor memory device having a wide data bus of an (m&times;n)-bit width can be considerably reduced.

Method of testing a semiconductor memory device

A semiconductor integrated circuit device includes an SDRAM module operating in synchronization with a clock signal, a logic circuit transmitting data with the SDRAM module for effecting necessary processing, a direct memory access circuit taking in and transferring an externally applied signal in synchronization with the clock signal corresponding to an operation clock of the SDRAM module, and a selector selecting either the output signal of the logic circuit and the output signal of the direct memory access circuit in accordance with a test mode instructing signal for application to the SDRAM module. A test of a synchronous memory can be performed by externally making fast and direct access to the synchronous memory without an influence of a skew in a signal.

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Hyogo, Japan

Atsuo Mangyo