Ricoh Company, Ltd.

Atsuo Hashimoto

Sugitaka Oteki

Takahiro Watanabe

Toshiyuki Furuta

Hirotoshi Eguchi

Hiroyuki Horiguchi

Toshihiro Tsukagoshi

Shuji Motomura

Satoshi Otsuki

Eiki Aono

Yutaka Ebi

Yoshio Watanabe

Takashi Kitaguchi

Tatsuya Furukawa

In a neural network configured of neuron model cells, each neuron model cell is adapted to hold an input signal when a forward process is performed and to hold an error signal inputted when a learning process is performed. The signal processing apparatus is arranged to execute the forward process and the learning process in parallel.

Signal processing apparatus using a hierarchical neural network

A neuron unit processes a plurality of input signals and for outputs an output signal which is indicative of a result of the processing, and includes input lines for receiving the input signals, a forward process part including a supplying part for supplying weight functions and an operation part for carrying out an operation on each of the input signals using one of the weight functions and for outputting the output signal, and a self-learning part including a function generating part for generating new weight functions based on errors between the output signal of the forward process part and teaching signals and a varying part for varying the weight functions supplied by the supplying part of the forward process part to the new weight functions generated by the generating part. The supplying part includes a memory for storing each weight function in the form of a binary value, and a generating circuit for generating a random pulse train based on each binary value stored in the memory. The random pulse train describes each weight function in the form of a pulse signal having a pulse density.

Neuron unit

A neuron unit processes a plurality of binary input signals and outputs a neuron output signal which is indicative of a result of the processing. The neuron unit is provided with a plurality of first gates respectively for carrying out a logical operation on a binary input signal and a weighting coefficient, a second gate for carrying out a logical operation on an excitatory output signal of each of the first gates, a third gate for carrying out a logic operation on an inhibitory output signal of each of the first gates, a fourth gate for synthesizing output signals of the second and third gates and outputting the neuron output signal, and a generating circuit for generating the weighting coefficients which are supplied to each of the first gates. The generating circuit for generating one weighting coefficient includes a random number generator for generating random numbers, and a comparator for comparing each random number r with a predetermined value q and for outputting a pulse signal having first and second values depending on whether each random number r is such that r.ltoreq.q or r&gt;q, and each weighting coefficient is described by a pulse density.

Neuron unit and neuron unit network

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Nishinomiya, Japan

Atsuo Hashimoto