Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Mitsubishi Electric Engineering Company, Limited

Other

Renesas Electronics Corporation

Atsuo Hanami

Satoshi Kumaki

Tetsuya Matsumura

Kazuya Ishihara

Hiroshi Segawa

Shinichi Nakagawa

Yoshinori Matsuura

Shinichi Uramoto

Shinichi Masuda

Kiyofumi Kawamoto

Stefan Scotzniovsky

Vasile Mosneaga

An overall motion detecting device () includes a search region variable-shaped motion detector () and an overall motion information generator (). The overall motion information generator () controls a surveillance camera () which is an external image capturing system and supplies control information of the surveillance camera () (such as moving direction, angular speed and focal length) to the search region variable-shaped motion detector () as overall motion information (S). The search region variable-shaped motion detector () calculates a motion vector (mv) while renewing, by picture, a search region having a search shape determined by the overall motion information (S) and a region area suitable for its operational capability.

Motion detecting device and search region variable-shaped motion detector

The control circuit controls output of template block data held in the input section such that a plurality of operation units within the operation section are provided with data of unadjacent template blocks that are different from each other. The operation units within the operation section detect motion vectors according to the template block data provided thereto. Thus, motion vector detection in the template blocks except for those in a region on a display screen requiring no motion vector detection is distributed in the plurality of operation units. Accordingly, the motion vector search can be performed in a wider range in a vertical or horizontal direction than in the conventional case within the same operation time.

Motion vector detecting device improved in detection speed of motion vectors and system employing the same devices

When the CPU writes data into a memory, a 0 detection circuit detects the number of bits having the value 0 from the data. When the number of bits with 0 is equal to or larger than the number of bits with 1, the data output from the CPU is provided to the memory under control of a selector. When the number of bits with 0 is fewer than the number of bits with 1, the data output from the CPU is inverted and provided to the memory under control of the selector. Accordingly, the rewriting frequency of each memory cell from 0 to 1 or from 1 to 0 in the memory can be reduced in average. Thus the power consumption of the memory in a data writing mode can be reduced.

Data processor and data processing method reduced in power consumption during memory access

Introduced in an image data encoding device is a logic-memory combined chip in which a memory device and a signal processing device are combined. A logic part and a memory part can be connected to each other with a wide bus, allowing to improve processing capability of data transfer. However, the memory part of the logic-memory combined chip has a small capacity, so that an attempt to increase the capacity will lead to upsizing of the chip, resulting in an increase in costs. Therefore, in a processing that data transfer results in bottlenecks (i.e., motion search), image data is transferred to/from an internal memory capable of transferring data at high speed. In a processing that high-speed data transfer is not required, image data is transferred to/from an external memory.

Image data encoding device

A plurality of motion detecting units of which at least a template block size, i.e., the number of estimation pixels, or a search area size is different among the motion detecting units are used adaptively according to the characteristic of, or the prediction coding type of, a target picture. This enables efficient motion vector detection to be accomplished without increasing the amount of hardware or power consumption.

Motion vector detecting apparatus

A processor array includes element processors which are arranged in a matrix in correspondence to respective pixels of a template block, which is a current picture image pixel block. Each element processor stores pixel data of a search window block, which is a corresponding reference picture image pixel block, and obtains an evaluation function value component with respect to the template block pixel data. A summing part sorts the evaluation function components received from the respective element processors of the processor array in accordance with a plurality of predictive modes and sums up the components for the respective sorts, for forming evaluation function values for the respective predictive modes. A comparison part compares the evaluation function values received from the summing part for each predictive mode, to decide a displacement vector providing the best similarity as a motion vector for each predictive mode. It is possible to simultaneously detect motion vectors according to a plurality of predictive modes. It is possible to detect motion vectors employed for moving image predictive compensation in accordance with a plurality of predictive modes at a high speed with a small hardware volume.

Motion vector detecting device capable of accommodating a plurality of predictive modes

Element processors (PE to PE ) included in a processor array ( ) store pixel values of a search window, shifting them forward. Further, only hatched element processors (PE , PE , PE , PE , PE , PE , PE , PE ) store pixel values of a template block, and compare them with the pixel values in the search to evaluate a similarity of pixel values. In other words, the pixel values of the template block are skipped and the pixel values which are left after skipping are compared. Therefore, it is possible to cut a hardware volume.

Motion vector detecting device

Disclosed is an image coding method and apparatus for preventing a coding quantity of coding data from being increased when a redundancy between image planes is low. A selector outputs either an optimum motion vector output from a motion vector detecting device or a motion vector output from a motion vector storing section to a real time image coding device for performing coding on the basis of an evaluation value output from the motion vector detecting device. If it is decided, according to the evaluation value, that a redundancy between a reference image plane and a coding object image plane is low, the motion vector is selected so that the coding quantity of the coding data can be prevented from being increased.

Image coding method and apparatus

Screen data consists of two sets of field data. Each set of field data is divided into a plurality of data blocks which has four rows of pixel data corresponding to four rows of pixels vertically arranged. Every data block corresponding to one set of field data is stored in the first bank (bank0) of a frame buffer memory while that corresponding to the other set of field data is stored in the second bank (bank1). One row address is assigned to each data block. Bank1 is precharged while bank0 is in a write operation and vice versa in order to carry out the precharging operation and the write operation concurrently, so that the pixel data can be transferred at a high data transfer rate and each of two sets of field data can be transferred independently.

Image process apparatus having a storage device with a plurality of

An evaluation value operation part computes evaluation values of a template block and a search window block in accordance with respective ones of a plurality of predictive modes in parallel with each other, and a candidate vector determination part decides candidate vectors indicating optimum vectors in accordance with the computed evaluation values and on the basis of priority levels from a priority generation part. In accordance with these candidate vectors, an optimum vector decision part decides the optimum vectors for the respective predictive modes. Thus provided is an image coding system which can reduce the amount of codes of motion vectors with excellent picture quality.

Motion vector detector

Each of element processors arranged in correspondence to pixels of a template block and a search window block respectively includes an A register and a B register provided in parallel with each other for storing search window block pixel data respectively, and a T register for storing template block pixel data. Motion vector evaluation value calculation is performed through a first one of the A and B registers and the pixel data stored in the T register, while operated data is transferred to the second one of the A and B registers from the first one of the A and B registers in parallel with the calculation operation, for storing head search window block pixel data of a next search window. A motion vector is detected at a high speed in excellent coding efficiency.

Unit for detecting motion vector for motion compensation

A first pseudo random number generating circuit sequentially provides an output signal to a matching detecting circuit in response to a clock signal. A second pseudo random number generating circuit generates an initial value, and then, sequentially provides an output signal to a storage device in response to an output signal from the matching detecting circuit and the clock signal. Data with the output signal as an address is provided as an output signal from the storage device. When the matching detecting circuit detects matching between the output signals, the matching detecting circuit provides the output signals to the second pseudo random number generating circuit and an AND logic circuit. As described above, when the output signal of the matching detecting circuit is provided, the output signals from the storage device are provided as respective output control signals.

Control signal generating device generating various control signals

Instructions of a program are stored at addresses sequentially designated in accordance with an M series pseudo-random number sequence in an instruction memory in the order of program addresses. A pseudo-random number program counter has a feedback shift register for generating the same M series pseudo-random number sequence and applies an address of an instruction to be read from the instruction memory to the instruction memory based on a generated pseudo-random number, and a jump address and a select signal from an instruction decoder. As a result, instructions are read from the instruction memory and executed in the order of program addresses. The feedback shift register can be implemented as a small-scale circuit and operable at high speed.

Program execution control device having addressability in accordance

A variable-length code table, which is used for producing a variable-length code from data formed of one set of first and second equal-length components, stores at an address uniquely assigned by the one set of the equal-length components a corresponding variable-length code and a code length of the variable-length code. Combination of the first and second equal-length components is preselected such that the maximum value of the absolute value of the first equal-length component increases as the absolute value of the second equal-length component combined therewith decreases. The second equal-length components are classified into a plurality of classes in accordance with the magnitude of the absolute value. Each address includes a first region having a value and a length uniquely specified based on the class including the second equal-length component, a second region storing the first equal-length component, and a third region storing the second equal-length component, and is constructed to have a fixed length as a whole. Region lengths of the second and third regions are determined correspondingly to the class including the second equal-length component, and each are specifically determined to have the minimum value required for storing the maximum values of the absolute values of the first and second equal-length components of the combinations of the equal-length components included in the corresponding class.

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Hyogo, Japan

Atsuo Hanami