Hitachi, Ltd.

Atsumi Kawata

Hiroki Yamashita

Hiroyuki Itoh

Hirotoshi Tanaka

Kenji Nagai

Kazuhiro Yoshihara

Minoru Yamada

Ichiro Imaizumi

Keiichirou Nakanishi

Tatsuya Saitoh

Fusaaki Kozawa

Tsuneyo Chiba

Nobuhiro Taniguchi

Takahiro Shimoirisa

Rieko Ishida

The present invention is provided a structure for mounting a printed board in which each connector that is attached to each of a plurality of sub printed boards, which are juxtaposed to one another with respect to a main printed board secured to a metal backboard, is inserted into each of a plurality of connectors that are juxtaposed to one another on the main printed board so that the sub printed boards are mounted on the main printed board by the connector connections. Parts of both ends of an area in proximity to a semiconductor-device mounted area on each of the sub printed boards ate pinched between a first metal frame and a second metal frame so that each of the sub printed boards are secured.

Structure for mounting printed board and nuclear medicine diagnosis system

In signal transmission lines among logic circuits employed in a semiconductor integrated circuit device, a voltage driver circuit is provided with such a wiring whose length is short, and the function of the signal receiving circuit is achieved by a logic circuit capable of responding to a voltage appearing at a terminal of the wiring. On the other hand, a source terminal of such a wiring whose length is long and whose resistance is high, is voltage-driven by the voltage driver circuit in response to the output voltage of the logic circuit. A current sense circuit is provided with a terminal of this long length wiring, which senses a current flowing through this long length wiring to be converted into a voltage. Both an output resistance of the voltage driver circuit and an input resistance of the current sense circuit are made lower than a DC resistance of this long length wiring.

Integrated circuit device having different signal transfer circuits for

A shift register 10 receives serial data and outputs parallel data in synchronism with the timing of the serial data received. A shift register group 20, 21 receives bit outputs of the parallel data from the shift register 10. The number of bits of shift registers 20, 21 in the shift register group is set in a certain condition that corresponds to the bit outputs of the parallel data from the shift register 10. A plurality of coincidence circuits 107, 108 are provided, which detects agreement between a preset data starting pattern and the bit arrangement of the data in the shift register group. A selector 306 selects a set of parallel outputs from the shift register group according to the output signal from the coincidence circuits 107, 108. Thus only the shift register 10, performs high-speed operations at the same timing as the received serial data, and the other circuits operate at slower speeds whose timing is several times longer than that of the serial data received, thereby eliminating complex timing and averting difficulty control logic.

Serial to parallel data converting circuit

A flip-flop circuit receives a pair of complementary data signals, then outputs complementary signals corresponding to the pair of complementary data signals. The pair of data signals are also supplied to a driving gate means which outputs a signal corresponding to at least one data signal of the pair of data signals supplied thereto. The driving gate means also comprises at least one try-state gate controlled by a clock signal. An output signal of the driving gate means is held by a memory means, and also outputted as complementary output signals.

Flip-flop circuit

A logic circuit, most suitable for the NOR gate, logic function and integration on a single chip with a plurality of such logic circuits and other digital circuits receiving the outputs of the logic circuits and the logic circuits themselves connected and cascade, wherein plural groups of input transistors are provided, with a load through the voltage source and one of the groups, field effect transistor between the voltage source and the other group, so that its gate is connected to the node between the load and first group and its source is connected to the output terminal, with the improvement being in finding a leakage load for the field effect transistor through the voltage source, providing a clamping circuit for the gate of the transistor. The clamping circuit can include a transistor having its gate connected to the output with a delay so that it will not come on until after a substantial portion of the rise time of the output has expired. An additional logic output may be taken from the gate of this transistor, preferably through a transistor to match the outputs, so that the logic circuit is provided with two independent outputs useful for providing adjacent logic or digital circuits with a conveniently close terminal for input, and further to take advantage of the isolation of the outputs by providing other directions for both outputs for circuit elements that must remain isolated, for example in cross coupling two logic circuits as a flipflop. One or more of the may be a field effect transistor, particularly provided with boot strapping. For otherwise identical logic circuits as a part of an overall integrated logic circuit, the clamping circuits may differ only with respect to matching respective output voltages or respective output currents with respective fan outs or other characteristics of load circuits to be driven by the outputs. Preferably, all of the elements are constructed of field effect transistors.

Logic circuit

Growing community of inventors

Hiratsuka, Japan

Atsumi Kawata