Fujitsu Corporation

Fujitsu Semiconductor Limited

Fujitsu Microelectronics Limited

Atsumasa Sako

Hiroyuki Kobayashi

Atsushi Takeuchi

Toshiya Miyo

A semiconductor storage device includes a memory cell array in which a memory cell including an MOS capacitor is arranged; a power supply unit that supplies a plate voltage to a plate line that is coupled to a gate electrode of the MOS capacitor; and a switch that couples the plate line to a first power supply line when an access to the memory cell array is caused.

Semiconductor storage device

A current mirror circuit which is connected to first and second power supplies and generates a desired current, has a plurality of first transistors which are connected in parallel to the first power supply side and the gates of which are connected to a common node, a plurality of second transistors which are cascode-connected to the plurality of first transistors and the gates of which are supplied with a cascode bias potential and a cascode bias generation circuit which generates the cascode bias potential, wherein the cascode bias generation circuit maintains the cascode bias potential during normal operation at a first potential between the potentials of the first and second power supplies, and maintains the cascode bias potential during power-on at a second potential closer to the potential of the second power supply than the first potential.

Internal power supply circuit having a cascode current mirror circuit

A disclosed invention is an internal power supply circuit, which generates an internal power supply from a first power supply. The circuit comprises a first internal step-down power supply generation unit, which generates a first internal step-down power supply from the first power supply; a normal second internal step-down power supply generation unit, which generates a second internal step-down power supply from the first internal step-down power supply in the normal operating state, and which, at the time of power supply startup, begins operation to generate the second internal step-down power supply at a first timing at which a voltage of the first internal step-down power supply reaches a prescribed reference level; and, a startup power supply load unit, which begins to consume, before the first time, current from the first internal step-down power supply.

Internal power supply circuit

A temperature detector sets the level of a temperature detecting signal to a level indicating a high temperature state, detecting that the chip temperature is higher than a first boundary temperature. The temperature detector sets the level of thereof to a level indicating a low temperature state, detecting that the chip temperature is lower than a second boundary temperature. A control circuit changes its operating state according to the level of the temperature detecting signal. This prevents the operating state of the control circuit from frequently switched even when the chip temperature fluctuates around the boundary temperatures, and accordingly reduces current consumption of the control circuit due to the switching operation. Further, the first and second boundary temperatures set a buffer zone, so that the temperature detector does not detect power supply noises as temperature variation. This can prevent malfunction of the temperature detector and the semiconductor integrated circuit.

Semiconductor integrated circuit

A semiconductor memory device is provided for minutely changing a refresh interval according to a detected temperature and thereby lowering its power consumption. A temperature detector detects a temperature of a chip and outputs the corresponding temperature signal. A reference temperature signal output unit outputs the corresponding reference temperature signal with each of different reference temperatures to be compared with the chip temperature according to a selection signal. A temperature comparison unit compares the chip temperature with the reference temperature through the temperature signal and the reference temperature signal. A selection signal output unit outputs the selection signal according to the compared result of the temperature comparison unit. A refresh interval control unit changes the refresh interval according to the compared result of the temperature comparison unit.

Semiconductor memory device

In addition to a booster power supply circuit boosting a power supply voltage to supply a boost voltage VPP to a memory core, cell capacitors composing a stabilization capacitor, and a bias generation circuit supplying a midpoint potential to a connection point of the cell capacitors, further, a clamp circuit reducing the boost voltage to a set value is provided, in which when the booster power supply circuit stops a boosting operation, the clamp circuit cramps the boost voltage to the set value, so that the midpoint potential can be prevented from largely deviating to a boosting voltage side and a ground potential side in a transition to a normal operation thereafter.

A semiconductor device temperature sensor produces a reference level for temperature detection from two or more reference levels of different temperatures to detect a temperature. The temperature sensor is applied for detecting the temperature of a semiconductor storage device having a memory unit which requires a refresh action. A refresh cycle control circuit provided in the semiconductor storage device controls the cycle of the refresh action for the memory unit in response to an output of the temperature sensor.

Semiconductor device temperature sensor and semiconductor storage device

A semiconductor memory device includes a memory cell array in which a plurality of memory cells for storing data are arranged, a sense amplifier for amplifying the data in the memory cell, a first power source, and a second power source lower than the first power source. In a first step, the sense amplifier receives power supply from the first power source to amplify the data in the memory cell. In a second step, the sense amplifier does not receive power supply either from the first power source or from the second power source. In a third step, the sense amplifier receives power supply from the second power source to amplify the data in the memory cell.

Semiconductor memory device and method of controlling the same

The variable delay circuit has a delay circuit and a selector. The delay circuit is formed of a plurality of delay stages connected in cascade. The delay circuit receives an input signal at the initial delay stage and respectively outputs a delayed signal which is the input signal delayed, from the delay stages. The selector receives the delayed signals and selecting signals respectively corresponding to the delayed signals. The selector selects the delayed signal corresponding to an activated selecting signal and outputs the selected signal as a delayed output signal. The delay stage(s) subsequent to the delay stage outputting the delayed signal selected by the selector is/are inactivated. Not operating unnecessary delay stages can prevent wasteful power consumption.

Growing community of inventors

Kawasaki, Japan

Atsumasa Sako