Nec Electronics Corporation

Nec Corporation

Atsuko Kozai

Takeshi Matsumoto

Isao Nakatsu

In a placement and routing for a standard cell type LSI design, each standard cell comprises a VDD power supply terminal formed of a P-type diffused layer, a VSS power supply terminal formed of an N-type diffused layer, and an input terminal and an output terminal formed of a first level metal. A plurality of standard cells are located to form a standard cell array, and VDD and VSS power supply lines formed of the first level metal are located to extend along opposite sides of the standard cell array, respectively. For connecting the power supply terminal of the standard cell to the power supply line of the first level metal, a power supply line formed of the diffused layer is extended from the power supply terminal to the power supply line of the first level metal, and a contact bole is formed at an overlapping portion between the power supply line of the first level metal and power supply line formed of the diffused layer. Thus, it is possible to place and route standard cells having different widths with no hindrance, and it is also possible to form an inter-cell connection in the device formation region between the power supply line and the wiring area within the cell. In addition, it is possible to set the width of the power supply line of the first level metal to an appropriate width for each standard cell array.

Standard cell, standard cell array, and system and method for placing and routing standard cells

A computer-aided design supporting system for a semiconductor device includes a cell library, an arranging tool and a wiring tool. The cell library stores a plurality of logic cell patterns, a plurality of power supply cell patterns, and a plurality of ground cell patterns. A logic device pattern of the semiconductor device includes one of the plurality of logic cell patterns, one of the plurality of power supply cell patterns, and one of the plurality of ground cell patterns. The arranging tool arranges selected ones of the plurality of logic cell patterns, selected ones of the plurality of power supply cell patterns and selected ones of the plurality of ground cell patterns on cell tracks individually and independently in response to an arrange instruction. The wiring tool connects between the selected logic cell patterns, between the selected power supply cell patterns and between the selected ground cell patterns arranged on the cell tracks in response to a wiring instruction to form a pattern of the semiconductor device.

Computer-aided design supporting system in which cells can be arranged independently

The present invention provides a semiconductor integrated circuit device, a layout design method and apparatus thereof which enable to select an arbitrary number of grids in primitive cells and minimize the layout area. Each primitive cell is constituted by a core portion having a circuit for realizing a function inherent to the primitive cell and a power supply wiring portion for electrical connection between the core portion and a power supply wiring and electrical connection between cores of different primitive cells. A primitive cell small group is prepared from a plurality of primitive cells having an identical core portion and different numbers of allocatable signal lines in the power supply wiring portion, so that a primitive cell having an appropriate number of signal lines as the power supply wiring portion is selected for layout.

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Kanagawa, Japan

Atsuko Kozai