Taiyo Yuden Co., Ltd.

Atsuhiro Yanagisawa

Yoshinori Shibata

Mikio Tahara

Daisuke Iwai

Hiroyuki Moteki

Takeshi Nosaki

Masumi Ishii

Michio Oshima

Haruna Ubukata

Tomonori Yamatoh

Satoko Namiki

A multilayer ceramic capacitor includes: a multilayer chip having a parallelepiped shape in which each of a plurality of dielectric layers and each of a plurality of internal electrode layers are alternately stacked and each of the internal electrode layers is alternately exposed to two end faces of the multilayer chip, a main component of the plurality of dielectric layers being a ceramic; and a pair of external electrodes that are formed on the two end faces; wherein: the pair of external electrodes have a structure in which a plated layer is formed on a ground layer; a main component of the ground layer is a metal or an alloy including at least one of Ni and Cu; and at least a part of a surface of the ground layer on a side of the plated layer includes an interposing substance including Mo.

Multilayer ceramic capacitor with interposing molybdenum (Mo) ground layer

A multilayer ceramic capacitor includes: a multilayer chip in which each of dielectric layers and each of internal electrode layers are alternately stacked and the internal electrode layers are alternately exposed to two end faces; and external electrodes formed on the two end faces; wherein: the external electrodes have a structure in which a plated layer is formed on a ground layer including Mo; and 'M&#x2265;0.003185&#xd7;(Ew&#xd7;Et)&#x2212;is satisfied when 'Et' is a height from a bottom one of the internal electrode layers to a top one of the internal electrode layers, &#x201c;Ew' is a width of the internal electrode layers in a direction in which side faces of the multilayer chip face with each other, and &#x201c;M&#x201d; is a Mo concentration (atm %) with respect to a main component ceramic of a total of the multilayer chip and the pair of external electrodes.

Multilayer ceramic capacitor using molybdenum (Mo) ground layer and manufacturing method of the same

A multilayer ceramic capacitor includes: a ceramic multilayer structure having a structure in which each of ceramic dielectric layers and each of internal electrode layers are alternately stacked and are alternately exposed to two edge faces of the ceramic multilayer structure, a main phase of the plurality of ceramic dielectric layers having a perovskite structure that includes Ca and Zr and is expressed by a general formula ABO; and a pair of external electrodes that are formed on the two edge faces, wherein 300&#xd7;TE/TA&#x2212;12&#x2264;30 is satisfied when a volume TA is a length C&#xd7;a width C&#xd7;a thickness Cof the ceramic multilayer structure and a volume TE is a length E&#xd7;a width E&#xd7;a thickness E&#xd7;a stacked number of the plurality of internal electrode layers in a capacity region.

Multilayer ceramic capacitor, circuit substrate and manufacturing method of the same

A multilayer ceramic capacitor includes: a multilayer chip in which each of dielectric layers and each of internal electrode layers are alternately stacked and the internal electrode layers are alternately exposed to two end faces; and external electrodes formed on the two end faces; wherein: a relationship 'M&#x2265;&#x2212;0.00002&#xd7;EM+0.0012' is satisfied, when a length of end margins in a direction in which the two end faces face with each other is EM [&#x3bc;m] and a ratio of Mo [atm %] to a B site element [atm %] of a main component ceramic in the end margins is M, wherein the end margin is a region, in which internal electrode layers connected to one of the external electrodes without sandwiching internal electrode layers connected to the other of the external electrode, face with each other, in the multilayer chip.

Multilayer ceramic capacitor and manufacturing method of the same

A multilayer ceramic capacitor includes: a multilayer chip having a parallelepiped shape in which each of a plurality of dielectric layers and each of a plurality of internal electrode layers are alternately stacked and are alternately exposed to two edge faces of the multilayer chip, a main component of the plurality of dielectric layers being a ceramic; and a pair of external electrodes that are formed on the two edge faces; wherein: the pair of external electrode have a structure in which a plated layer is formed on a ground layer; a main component of the ground layer is a metal or an alloy including at least one of Ni and Cu; and the ground layer includes Mo.

Growing community of inventors

Takasaki, Japan

Atsuhiro Yanagisawa