Fujitsu Corporation

Atsuhiro Suga

Hideo Miyake

Yasuki Nakamura

Teruhiko Kamigata

Satoshi Imai

Hiroshi Okano

Yoshimasa Takebe

Hitoshi Yoda

Takuya Iwata

Tsutomu Tanaka

Shigeru Kimura

Shinichiro Tago

Toshihiro Ozawa

Yoshio Hirose

Makiko Ito

Taizo Sato

Fumihiko Hayakawa

Hideki Sakata

Yasuhiro Yamazaki

Kazuhide Yoshino

Akitoshi Ino

Hitoshi Miyaoku

Michihide Kimura

Shin-ichiro Tago

Koichi Sasamori

To provide a program performance analysis apparatus that can present to a user whether tuning made to a program operating on a predetermined hardware is either good or bad, a performance information acquisition unit for obtaining the performance information of a program, a difference information generation unit for generating difference information by making a comparison between the performance information of a first program and that of a second program obtained by making a change to the first program, and a change evaluation unit for evaluating whether the change is either good or bad are comprised.

Program performance analysis apparatus

According to one aspect of embodiments, a multiprocessor system includes a cache memory corresponding to each of the processors, a hierarchy setting register in which the hierarchical level of each cache memory is set, an access control unit that controls access between each cache memory. The hierarchical level of the cache memory for each processor is stored in a rewritable hierarchy setting register. Each processor handles a cache memory corresponding to another processor as the cache memory having a deeper hierarchy than the cache memory corresponding to the each processor. As the result, each processor can access all the cache memories, and therefore the efficiency of cache memory utilization can be improved and the hierarchical level can be set so that the latency becomes optimal for each application.

Multiprocessor system and operating method of multiprocessor system

A dependent element group which is invertibly contractible is found by using program analysis information including a plurality of dependent elements representing dependent relationships of statement and control, the statement and the control being included in a program. Next, a program dependence graph in which dependent elements are made to be contracted is generated by contracting the found dependent element group. The number of vertices and the number of edges of the program dependence graph are reduced by the contraction of the dependent elements, so that a program dependence graph with a rough granularity can be generated. As a result, a calculation amount (calculation time) necessary for optimization processing such as parallel processing of the program can be reduced. That is, by generating the contracted program dependence graph having invertibility, it is possible to realize the analysis and optimization of large-scale software in a realistic time.

Method and apparatus for analyzing large scale program and generation of code from degenerated program dependence graph

When a normal interrupt occurs, data of processor operation before the normal interrupt are held in a normal return address register (), a normal previous state register (), and a normal factor register (). When a break-interrupt occurs, data of processor operation before the break-interrupt is held in another break return address register (). Hence, a break-interrupt can occur even within an interrupt inhibition period by a normal interrupt. Besides, when a break-interrupt occurs, the break-interrupt state is set in a flag register (). By referring to the flag register () in executing an interrupt return instruction, the operation data before the break-interrupt or before the normal interrupt can accurately be restored.

Interrupt control apparatus and method

A parallel processor performs efficient parallel processing of one or more basic instructions contained in each of a plurality of instruction words delimited by instruction delimiting information. The processor includes: a plurality of instruction execution units performing processes in accordance with corresponding, supplied basic instructions in parallel; an instruction fetch unit fetching the instruction words one by one in accordance with the instruction delimiting information; and an instruction issue unit recognizing and, in accordance therewith, selecting each of the basic instructions contained in each of the instruction words fetched by the instruction fetch unit to a corresponding instruction execution unit to execute the basic instruction.

Parallel Processor efficiently executing variable instruction word

In the control section, an operation instruction not prescribing a functional specification, and a unit for processing the specific application-purpose operation instruction is provided within the processor core. The structure of this unit can be changed based on a flexible pipeline structure, and is separately designed for each application field. A register that prescribes a latency from when an instruction of the above unit is issued till when a result can be utilized is also provided in the processor core so as to prevent contention of an output port. Another register that prescribes a latency relating to a constraint of an interval of issuing an instruction of the above unit is also provided in the processor core so as to prevent contention of a resource with the preceding instructions.

Information processing unit, and exception processing method for specific application-purpose operation instruction

An information processing device reads, buffers, decodes and executes instructions from an instruction store portion by pipeline processing includes: an instruction reading request portion which assigns a read address to the instruction store portion, an instruction buffering portion which includes a plurality of instruction buffers which buffer an instruction sequence read from the instruction store portion; an instruction execution unit which decodes and executes instructions buffered by the instruction buffering portion. A branching instruction detection portion detects a branching instruction in the instruction sequence read from the instruction store portion. A branch target address information buffering portion includes a plurality of branch target address information buffers which, when the branching instruction detection portion has detected a branching instruction, buffer the branch target address information for generating the branch target address of the branching instruction.

Processing device for buffering sequential and target sequences and target address information for multiple branch instructions

When an input address AD is previously stored in a register, if a matching signal EQis active, then an address queue control circuitA latches an offset of the input address AD into a register, or else, latches the input address AD into a registerthrough a selector. When the input address AD is previously stored in the register, the address queue control circuitA latches the input address AD into the registerthrough the selector. After reading the contents of the register, the address queue control circuitA shifts the offset OFS of the registerto the offset field of the registerthrough a selector, and resets a valid flag EF of the register

Information processing device equipped with improved address queue register files for cache miss

The present invention relates to a processor that performs a load operation prior to a store operation while avoiding ambiguous memory reference, and achieves high-speed operations. The present invention also relates to a method of controlling such a processor. This processor includes a history control unit that stores a storage destination of a result obtained by executing a second instruction that is executed prior to a first instruction placed before the second instruction. When it is determined that the address of first data to be processed by the first instruction is included in the address region of second data to be processed by the second instruction, the history control unit overwrites the result obtained by the execution of the first instruction on the second data corresponding to the address.

Processor and method of controlling the same

In a cache memory control method and computer of the present invention, a cache memory is connected to a main memory and divided into a plurality of cache blocks, and a lock/unlock signal is supplied to the cache memory to either set a replace-inhibition state of at least one of the cache blocks in which replacing at least one of the cache blocks to the main memory is inhibited, or reset the replace-inhibition state of at least one of the cache clocks such that replacing at least one of the cache block to the main memory is allowed. Either reading or writing of the main memory is performed by using the remaining cache blocks of the cache memory, other than the at least one of the cache blocks, such that, when the replace-inhibition state is set by the lock/unlock signal, replacing the at least one of the cache blocks to the main memory is inhibited during the reading or writing of the main memory.

Method of Controlling and addressing a cache memory which acts as a random address memory to increase an access speed to a main memory

The present invention provides a processor system having a main processor that efficiently executes coprocessor instructions, regardless of the type of each coprocessor to which the main processor is connected. When a coprocessor instruction to instruct execution by a coprocessor is supplied, the main processor determines whether or not the supplied coprocessor instruction has a possibility of having control dependency on a preceding coprocessor instruction being executed by a corresponding one of the coprocessor, in accordance with an instruction field corresponding to the supplied coprocessor instruction. If the supplied coprocessor instruction has the possibility of having the control dependency, the main processor issues the supplied coprocessor to the corresponding one of the processors only after the execution of the preceding coprocessor instruction is completed.

Processor and processor system

When a normal interrupt occurs, data of processor operation before the normal interrupt are held in a normal return address register ( ), a normal previous state register ( ), and a normal factor register ( ). When a break-interrupt occurs, data of processor operation before the break-interrupt is held in another break return address register ( ). Hence, a break-interrupt can occur even within an interrupt inhibition period by a normal interrupt. Besides, when a break-interrupt occurs, the break-interrupt state is set in a flag register ( ). By referring to the flag register ( ) in executing an interrupt return instruction, the operation data before the break-interrupt or before the normal interrupt can accurately be restored.

Interrupt control apparatus and method separately holding respective operation information of a processor preceding a normal or a break interrupt

To an existing instruction set, newly added are a condition code conversion instruction for converting a first condition code (N, Z, OV, C) to a second condition code (V, S) based on a reference condition code COND, a second conditional instruction having a reference flag SF, and an instruction of operation between two selected second condition codes. A VLIW processor comprises a second condition code register file a condition code conversion circuit A, and a logic operation circuit E for performing a non-Boolean logic operation between two selected second condition codes.

Information processor

A data processing apparatus temporarily stores data to a cache write buffer and then stores the data in a cache storing device. The cache storage device performs a data storage operation with precedence over another operation even if a store instruction contends with a read instruction for accessing the cache storing device. A storage request low signal, sent from a cache write buffer controlling device to a cache controlling device, allows a read request to have precedence over a store instruction even when there is data stored in the cache write buffer waiting to be transferred to the cache storing device in response to the store instruction. However, when the read instruction contends with the store instruction and a state transition signal, such as an instruction cancellation signal generated from an instruction controlling device, is detected, the cache write buffer controlling device changes the output signal to a storage request high signal that causes the storage operation to have precedence over the read operation.

Data processing apparatus with a cache controlling device

An address buffer that stores information used to access a data memory is disposed in a cache unit that supplies data such as an instruction code to an instruction executing unit. A tag memory and a data memory are independently accessed. The data memory is accessed corresponding to access information stored in the address buffer. Data is output from the data memory in the input order of data requests. When a data release signal is not received from the instruction executing unit, since access information is buffered in the address buffer, a large data buffer for storing the output data of the data memory is not required. In addition, in an associative type cache unit, the tag memory and the address buffer can be formed in the same memory.

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Kawasaki, Japan

Atsuhiro Suga