Texas Instruments Corporation

Oki Semiconductor Co., Ltd.

Atsuhiro Miwata

Yoshinori Okada

Seiji Murakami

Manabu Nishimuzu

Toshiki Azuma

Atsushi Sudoh

A source driver includes a ladder circuit for outputting multilevel gradation voltages by resistance voltage division, a first decoder for selecting one gradation voltage corresponding to the inputted image data to output the selected gradation voltage, an external power supply for supplying multilevel pre-charging voltages, a second decoder for selecting one pre-charging voltage corresponding to the image data, an operational amplifier for outputting the driving voltage corresponding to the inputted gradation voltage to the source electrode, a pre-charging switch interconnected between the operational amplifier and second decoder, and a controller for controlling the pre-charging switch. The connection between the first decoder and operational amplifier is always kept during the whole sampling period including a pre-charging period, and the controller controls the pre-charging switch to be turned on during the pre-charging period and turned off after the pre-charging period has expired.

Display driving apparatus for charging a target voltage within a sampling period and a method therefor

A current driver that can control variation in the consumed current in conjunction with variation in the setting value of the driving current. The mirror current of transistors Q-to Q-at each of output circuits-to-keeps flowing through output terminal Toor node Nirrespective of the setting value of the pixel data. Also, the mirror current of transistor QD keeps flowing in the series circuit of transistors QD and QD irrespective of the setting value of the pixel data. Consequently, even when the setting value of the driving current varies in various ways, the current consumed in each output circuit can still be kept constant. As a result, it is possible to prevent variation in the voltage of the power supply line in conjunction with variation of the consumed current, and it is possible to reduce fluctuation in the driving current between output channels.

Current driver

A shift register with low power consumption has memory circuits - connected in series, gate circuits in memory circuits in the odd-numbered locations become conductive when clock signal CK is high, and gate circuits in memory circuits in the even-numbered locations become conductive when clock signal CK is low, wherein data signals S input are latched for output when the gate circuits are shut off. The circuit configuration is simplified. The Shift register operates every one half of the cycle of clock signal CK, allowing the frequency of clock signal to be reduced by half, resulting in reduced power consumption.

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Oita, Japan

Atsuhiro Miwata