Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Matsushita Electronics Corporation

Atsuhiro Kajiya

Hisashi Ogawa

Hiroaki Nakaoka

Kyoji Yamashita

Katsuhiro Ootani

Kentaro Nakanishi

Daisaku Ikoma

Yoshihiro Sato

Takayuki Yamada

Shin Hashimoto

Hiroyuki Sakai

Hiroyuki Umimoto

Satoshi Ishikura

Isao Miyanaga

Susumu Akamatsu

Kyoko Egashira

Takatoshi Yasui

A semiconductor device includes a first MIS transistor formed on a first active region, and a second MIS transistor formed on a second active region. The first MIS transistor includes a first gate insulating film, and a first gate electrode including a first metal film and a first silicon film. The second MIS transistor includes a second gate insulating film, and a second gate electrode including the first metal film, a second metal film, and a second silicon film.

Semiconductor device and method for fabricating the same

A semiconductor device includes a semiconductor substrate; a diffusion region which is formed in the semiconductor substrate and serves as a region for the formation of a MIS transistor; an element isolation region surrounding the diffusion region; at least one gate conductor film which is formed across the diffusion region and the element isolation region, includes a gate electrode part located on the diffusion region and a gate interconnect part located on the element isolation region, and has a constant dimension in the gate length direction; and an interlayer insulating film covering the gate electrode. The semiconductor device further includes a gate contact which passes through the interlayer insulating film, is connected to the gate interconnect part, and has the dimension in the gate length direction larger than the gate interconnect part.

Semiconductor device

A first semiconductor region has a smaller width along a gate length direction than a second semiconductor region. In this case, the first semiconductor region has a larger width along a gate width direction than the second semiconductor region.

In a semiconductor device according to the present invention, the power source voltage Vddof a core transistor Trthe power source voltage Vddof an I/O transistor Trand the power source voltage Vddof an I/O transistor Trsatisfy Vdd&#x3c;Vdd&#x3c;VddIn a method for fabricating the semiconductor device, each of the respective gate insulating films of the I/O transistors Trand Tris formed in the same step to have the same thickness. Each of the respective SD extension regions of the core transistor Trand the I/O transistor Tris formed at the same dose.

As first thermal treatment for activating an impurity injected into a gate electrode, thermal treatment at a low temperature for a long time in which boron diffusion into each crystal grain in polysilicon hardly occurs and boron diffusion in each crystal boundary occurs is performed. Next, as second thermal treatment, thermal treatment at a high temperature for a short time, such as spike annealing and flash annealing, in which impurity diffusion into each crystal grain in a polysilicon layer occurs is performed.

A single evaluation portion is formed by disposing a plurality of MIS transistors used for evaluation having substantially the same structure as that of an actually used MIS transistor. In the evaluation portion, the respective source regions, drain regions, and gate electrodes of the MIS transistors used for evaluation are electrically connected in common to a source pad, a drain pad, and a gate pad, respectively. If the effective gate width of the single evaluation portion exceeds a given value, variations in characteristics evaluated by the evaluation portion approach variations in the characteristics of the entire semiconductor device. The accuracy of evaluating the characteristics of the semiconductor device can thus be improved by using the evaluation portion.

Semiconductor device and method for evaluating characteristics of the same

A memory cell transistor and a planar capacitor are provided in a memory region, and both transistors of a CMOS device are provided in a logic circuit region. A capacitance dielectricand a plate electrodeof the planar capacitor are provided over a trench shared with a shallow trench isolationand the upper part of the trench is filled with the capacitance dielectricand the plate electrodeAn n-type diffusion layerthat is a storage node is formed, with an end region thereof extending along one side of the upper part of the trench, to a region of the substrate overlapping with the shallow trench isolationThe area of a part of the substrate functioning as a capacitor can be increased without increasing the substrate area.

Semiconductor device and its manufacturing method

A manufacturing method for a semiconductor device, whereby poly-silicon serving as an etching stopper is formed above a redundant fuse at the same time as a cell plate is. A silicon nitride film, an oxide film, and another oxide film on the redundant fuse are consecutively etched using the poly-silicon as the etching stopper. Then the poly-silicon is etched.

Method of forming a semiconductor device by using a conductive film as

In a semiconductor device, a FET and an isolation are provided on a semiconductor substrate and a channel stop region is provided under the isolation. At least a region to which a high voltage is applied of a source region and a drain region of the FET is separated from the channel stop region, and a first buffer region doped with an impurity for adjusting the threshold level is provided therebetween. A region under a gate electrode and adjacent to the isolation serves as a second buffer region to which an impurity for adjusting the threshold level is doped. With the first buffer region, a depletion region at a boundary of the drain region and the channel stop region is ensured, obtaining a superior durability to high voltage of the source/drain region. With the second buffer region, leakage current between the source region and the drain region is prevented.

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Hyogo, Japan

Atsuhiro Kajiya