Oki Electric Industry Co., Ltd.

Atsuhiko Okada

Satoru Tanoi

Shingo Kazuma

Hideaki Wada

Mitsuaki Watanabe

Hirosuke Tabata

Hajime Iwai

A transmission unit loads transmission data on a first register and outputs it to a transfer line and starts counting the transmission clock signals in a strobe generation counter according to a transmission clock signal. When the counted value reaches a set value, a strobe signal is output. A reception unit loads the transfer data onto a second register according to a reception clock signal. An edge detection unit generates a valid signal with a pulse width corresponding to one cycle of the reception clock signal when the strobe signal is detected. A third register loads the data that is output from the second register, and outputs it as reception data according to the reception clock signal when the valid signal is supplied.

Data transfer circuit

A mixed-voltage interface transfers signals serially between a pair of circuit blocks operating at different voltage levels in a semiconductor integrated circuit. Control, address, and data signals are multiplexed onto a common signal line. The number of necessary signal lines is thereby greatly reduced, as compared with parallel signal transfer, and a separate electrostatic discharge protection circuit can be provided for each signal line without the need to devote excessive space to protection circuitry.

Mixed-voltage interface and semiconductor integrated circuit

An interrupt signal EMG is put out to a microprocessorwhen a thermal monitordetects that a package temperature exceeds a reference. The microprocessor then increases a frequency division value N stored in a frequency division value registerof a clock mechanism. An inputted clock signal MCK is divided by N to generate a system clock signal SCK. Therefore, the frequency of system clock signal SCK decreases when N increases. Consequently, electricity consumption of each function modulei decreases and the package temperature is reduced.

Temperature controlled semiconductor circuit

A correlation value calculating device which has a small scale of circuitry, and allows template vectors to be rewritten. One template vector is written to one row of DRAM memory cells. One memory cell pair is used for storing one template vector component. A high-level is written to one memory cell and a low-level is written to the other memory cell according to the value of the template vector component. When calculating a correlation value, one memory cell of each memory cell pair is respectively connected to corresponding bit line according to the corresponding input vector component. If the components of both vectors are matched, the memory cell of the high-level is connected to the bit line, and if both vectors are not matched, the memory cell of the low-level is connected to the bit line. The electric potential of bit lines each become to indicate the correlation value.

Correlation value calculating device

In an amplifier having an input terminal to which input data is supplied and an output terminal from which output data corresponding to the input data is output, the input and output terminals are disposed between a power supply node to which a power supply is applied and a reference voltage node to which a reference voltage is applied. The output terminal and the reference voltage node are connected to each other and the input terminal and the output terminal are disconnected from each other, before the input data is supplied to the input terminal. The output terminal and the reference voltage node are disconnected from each other and the input terminal and the output terminal are connected to each other, after the input data is supplied to the input terminal.

Amplifier for a semiconductor device and a method of controlling the same

A semiconductor device that enables a reduction in power consumption and a stable operation, and which can be manufactured easily and with a high level of integration. In an invention exemplifying the present application, a sense circuit constituting a DRAM comprises a bit line pre-charge circuit, a pre-amplifier circuit PSA100 and a main amplifier circuit MSA100. The pre-amplifier circuit is provide with a switch circuit and an amplifier circuit. The switch circuit comprises a switch element provided between input/output terminals and a pre-sense node, and a switch element provided between input/output terminals and another pre-sense node. The amplifier circuit comprises MOS transistors and switch elements.

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Tokyo, Japan

Atsuhiko Okada