Kabushiki Kaisha Toshiba

Atsuhiko Nunokawa

Shiroshi Kanemitsu

Miho Iizuka

Makoto Monoi

Shin-ichi Imai

Kazuhide Sugiura

According to one embodiment, a solid-state imaging device includes a pixel array and AD converting unit. In the AD converting unit, a plurality of AD converts are arranged in a horizontal direction. The pixel is configured by a small pixel group. The small pixel group is formed of a plurality of small pixels. The plurality of small pixels read out the signal charges. The small pixel group includes two or more small pixels having different optical sensitivities. The solid-state imaging device includes N AD converting units. N is the number of small pixel groups which are arranged in a vertical direction at every small pixel. N is an integer of 2 or higher.

Solid-state imaging device and camera module including AD converting units for respective pixels

According to one embodiment, a solid-state imaging device includes a pixel array and a high dynamic range (HDR) synthesizing circuit. A pixel is configured as a small pixel group. The HDR synthesizing circuitincludes a valid pixel selecting unit, a sensitivity ratio correcting unit, and a calculation processing unit. The valid pixel selecting unitselects one or more small pixels validating a use of a signal value in the HDR synthesis as a valid pixel from among the small pixel group. The sensitivity ratio correcting unitexecutes sensitivity ratio correction on the signal value of each small pixel. The calculation processing unituses the signal value of the valid pixel among the signal values of the small pixels from the sensitivity ratio correcting unitfor a calculation for the HDR synthesis.

Solid-state imaging device and camera module

A CCD filter according to the present invention can provide good comb-shaped characteristics with no adjustments, and can be produced at low cost. The input section 15 of a first CCD 11 is constructed so that it can linearly reduce transferred charges when an input voltage increases. The input section 17 of a second CCD 12 is constructed so that it can linearly increase transferred charges when the input voltage increases. The transferred charges of the first and second CCDs 11 and 12 are added to each other by means of charge adder section 13, and the addition result is output from an output section 14.

CCD filter having comb-shaped characteristics

An input bias circuit employs a gate input type CCD register and an inversion-type amplifier. An output node of the inversion-type amplifier is connected to the input gate electrode of the CCD register, and an input signal to be biased is supplied to the input gate electrode. An output node of the inversion-type amplifier is connected to the floating diffusion region of the CCD register, and a signal charge is picked up from the floating diffusion region. A comparator performs comparison among the low level of the injection pulse supplied to the input diffusion region (which serves as an input diode), the potential level of the input signal supplied to the input gate electrode of the CCD register, and the level of the low-level generated by a low-level signal generating means. On the basis of this comparison, the potential level of the input signal of the CCD register is controlled such that it is higher than the low level of the injection pulse.

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Kanagawa, Japan

Atsuhiko Nunokawa