Vlsi Technology, Inc.

Athanasius W Spyrou

Arnold Ginetti

Michael N Misheloff

Michael D Grossman

Thomas J Schaefer

Francois Silve

Jean-Michel Fernandez

Clementina Bures

Marie C Salet

The present invention is directed to a method and apparatus for accurately estimating signal delays of an electrical circuit by taking into account both resistance and capacitance of an interconnect network when determining both gate delays and interconnect delays of the circuit. Exemplary embodiments of the present invention, by providing a highly accurate estimate of signal delays, result in highly efficient, cost-effective electrical circuit design and fabrication. Further, a high degree of customer satisfaction can be realized because the possibility that a given electrical circuit will not comply with customer specified time constraints is minimal.

Method and apparatus for verifying signal timing of electrical circuits

In a computer aided design system for assisting in the design and analysis of integrated circuits, users can specify an integrated circuit using either a conventional circuit component netlist, or an HDL circuit description. Timing constraints are specified using conventional system level timing constraints, at least one clock timing constraint and a plurality multi-cycle timing constraints specifying clock based timing constraints for the transmission of data between sequential data elements in which at least a subset of the clock based timing constraints concern timing constraints for duration longer than a single clock period. In addition, the user may provide the system with a plurality of constraint based timing path specifications, each indicating signal paths through the integrated circuit to which specified ones of the multi-cycle timing constraints are applicable and signal paths to which the specified ones of the multi-cycle timing constraints are not applicable. The computer aided design system then automatically verifies that the integrated circuit satisifies the specified timing constraints. During the timing constraint verification process, for mutli-clock timing constraints, signal arrival times and required signal arrival times are propagated and back-propagated only through signal paths consistent with the constraint based timing path specifications. In addition, the verified netlist, timing constraints and constraint based timing path specifications may be passed to a silicon compiler for automatically placing/routing a circuit in accordance with the netlist, timing constraints and constraint based timing path specifications.

Method and a system for specifying and automatically analyzing multiple

A computer aided design system converts system level timing constraints to the minimum number of path-based timing constraints necessary to represent the same timing constraints as the system level timing constraints. Using a data structure for each node of the circuit, signal arrival times and required arrival times for each node are generated for each high level timing constraint, and the worst slack time is identified for each node. Then, a node with a worst slack time is selected, the constraint associated with that worst slack time is identified, and then a worst case path from a start node of the identified constraint through the selected node to an end node of the identified constraint is determined. The start and required signal arrival times associated with the identified constraint's start and end nodes in the determined path are also identified. Then the determined path, and the maximum signal traversal time associated with that path are written to a path-based constraint data structure, and all the nodes in the determined path are marked as having been processed. Additional path-based constraints are generated, each time using an unmarked node having a worst remaining slack time, until all nodes in the circuit netlist having identified slack times have been included in at least one path-based constraint. The set of path-based constraints are used by a circuit layout generator to generate a circuit layout that meets the specified timing constraints.

Automated system and method for identifying critical timing paths in

The present invention is directed to a method of designing and fabricating a circuit layout which revolutionizes the manner by which critical weights of a circuit layout are assessed. In accordance with exemplary embodiments, a critical path is assessed on the basis of both a physical delay associated with a data propagation path and with respect to any clock skew which exists with respect to the data propagation path. A critical path can be a path having the shortest physical length from an input node to an output node if the clock skew along this path results in a high probability of a race condition. In accordance with exemplary embodiments, clock skew is assessed by determining the time differential between the arrival of a clock signal at a given data source instance and the arrival of a clock signal at a given data destination instance.

Method of finding a critical path in a circuit by considering the clock

The invention accepts user input that describes the circuit elements of a digital circuit and the interconnections between those elements. Based upon the user input, the invention computes the maximum setup and hold times for each data input of the integrated circuit. First, maximum and minimum delays from the clock inputs to the storage elements on the integrated circuit. Similarly, the maximum and minimum delays from the data inputs of the integrated circuit to each level one storage element are determined where a level one storage element is defined as a storage element that has no other storage elements interposed between it and a data input. For each data input/level one storage element pair, the setup time is computed based upon the previously calculated maximum data delay and minimum clock delay and the required setup time for the element. The desired setup time for a data input is the maximum setup time over all the level one storage elements coupled to that data input. Hold times are similarly determined except that the hold time is based upon the previously calculated maximum clock delay and minimum data delay and the required hold time for the element.

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San Jose, CA, United States of America

Athanasius W Spyrou