Advanced Micro Devices Corporation

Tesla, Inc.

Atchyuth Gorti

Daniel William Bailey

Bill K Kwan

Anirudh Kadiyala

Venkat Kuchipudi

Aditya Jagirdar

David Brian Glasco

Bill K C Kwan

Amit Pandey

Archana Somachudan

David A Kaplan

Grady L Giles

Eric C Quinnell

Norm M Hack

James A Wingfield

Bikash Kumar Agarwal

Salih Hamid

William Yang

Tendy The

A vehicular autonomous driving system includes a fault prediction unit, including a processor and memory, configured to predict a potential future fault condition by: monitoring performance data associated with the plurality of autonomous driving components; comparing the performance data associated with the plurality of autonomous driving components to a plurality of performance thresholds; and determining the potential future fault condition for one of the plurality of autonomous driving components, when the performance data associated with the one of the plurality of autonomous driving components compare unfavorably to corresponding one of the plurality of performance thresholds.

Autonomous driving system component fault prediction

A vehicular autonomous driving system includes a fault prediction unit, including a processor and memory, configured to predict a potential future fault condition by: monitoring performance data associated with the plurality of autonomous driving components; comparing the performance data associated with the plurality of autonomous driving components to a plurality of performance thresholds; and determining the potential future fault condition for one of the plurality of autonomous driving components, when the performance data associated with the one of the plurality of autonomous driving components compares unfavorably to a corresponding one of the plurality of performance thresholds.

A capture clock generation control mechanism is provided. The capture clock generation control mechanism controls the number of at-speed clocks generated and supplied to one or more scan chains during scan testing of a microcircuit based on control data stored in a JTAG or scan test register. The scan test register may be formed out of scan cells and comprise part of a scan chain. Automatic Test Pattern Generation (ATPG) tools may generate the data that is loaded into the scan test register to automatically configure the clock generation control mechanism. The clock control mechanism may include the ability to adjust the position of the at-speed clocks within a capture cycle, thereby facilitating transition fault detection.

Scan or JTAG controllable capture clock generation

A scalable, reconfigurable Memory Built-In Self-Test (MBIST) architecture for a semiconductor device, such as a multiprocessor, having a Master and one or more Slave MBIST controllers is described. The MBIST architecture includes a plurality of MBISTDP interfaces connected in a ring with the Master MBIST controller. Each MBISTDP interface connects to at least one Slave controller for forwarding test information streamed to it from the Master MBIST controller over the ring. Test information includes test data, address, and MBIST test commands. Each MBISTDP interface forwards the information to the Slave controller attached thereto and to the next MBISTDP interface on the ring. Test result data is sent back to the Master MBIST controller from the MBISTDP interfaces over the ring.

Memory bit MBIST architecture for parallel master and slave execution

We report methods relating to scan warmup of integrated circuit devices. One such method may comprise loading a scan test stimulus to and unloading a scan test response from a first set of logic elements of an integrated circuit device at a scan clock first frequency equal to a test clock frequency; adjusting the scan clock from the first frequency to a second frequency by a scan warmup unit, wherein the scan clock second frequency is equal to a system clock frequency; and capturing the scan test response by a shift logic at the scan clock second frequency. We also report processors containing components configured to implement the method, and fabrication of such processors. The methods and their implementation may reduce di/dt events otherwise commonly occurring when testing logic elements of integrated circuit devices.

Scan warmup scheme for mitigating di/dt during scan test

A test circuit for a functional circuit includes a scan chain coupled to the functional circuit, and a controller coupled to the scan chain, for controlling the scan chain to scan a test pattern into the scan chain, and subsequently and repetitively for a multiple number of times launch the test pattern to the functional circuit, capture test data into the scan chain, and restore the test pattern in the scan chain for subsequent launch.

Test circuit having scan warm-up

A circuit with built-in self test (BIST) capability includes a master BIST controller, a plurality of slave BIST controllers, and a collector. The master BIS controller issues test instructions in response to a master resume input signal. The plurality of slave BIST controllers is coupled to the master BIST controller. Each slave BIST controller is adapted to perform a test on a functional circuit in response to a test instruction and to provide a resume signal at a conclusion of the test. The collector receives a corresponding resume signal from each of the multiple slave BIST controllers after the master BIST controller issues the test instruction, and subsequently provides the master resume signal in response to an activation of all of the corresponding resume signals.

Scalable built-in self test (BIST) architecture

Scan-based reset utilizes already existing design-for-test scan chains to reset control and logic circuitry upon reset conditions, such as power-up reset. Such utilization eliminates the need for expensive, high fan-out reset trees and per scan cell reset control logic, thus reducing chip area and power consumption. Additional power savings is achieved by controlling clock frequency during reset conditions. Limiting scan cell chain length and providing multiple chains reduces reset latency.

Scan-based reset

The present invention provides a method and apparatus for saving and restoring soft repair information. One embodiment of the method includes storing soft repair information for one or more cache arrays implemented in a processor core in a memory element outside of the processor core in response to determining that a voltage supply to the processor core is to be disconnected.

Method and apparatus for saving and restoring soft repair data

A method, computer program storage device and apparatus are provided for flexible observability during a scan. In one aspect of the present invention, a method is provided. The method includes providing a selector load input to at least a portion of a scan chain, selecting an observe-only scan mode for the at least a portion of the scan chain based at least upon the selector load input, and providing a data input to a storage element in the scan chain based at least upon the observe-only scan mode. The apparatus includes a first scan chain multiplexor comprising a selector input, a first input terminal, a second input terminal and an output terminal. The apparatus also includes a first scan chain storage element comprising an input terminal and an output terminal, where the input terminal of the first scan chain storage element is communicatively coupled to the output terminal of the first scan chain multiplexor. The apparatus further recites that the output terminal of the first scan chain storage element is communicatively coupled to the first input terminal of the first scan chain multiplexor. The computer program storage device adapts a manufacturing facility to create the apparatus.

Configurable Mux-D scan flip-flop design

A method and apparatus to improve the efficiency of debugging a processor is provided. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create an apparatus. The method includes receiving a first test data, which identifies a state of a state machine, wherein the state machine performs reset and initialization operations for a processor. The method also includes halting the state machine in the state identified by the first test data upon reaching the state.

Enhanced debug/test capability to a core reset process

An integrated circuit () includes a debug module () and a clock generator (). The debug module () is configured to receive a test pattern and provide a mode signal based on the test pattern. The clock generator () includes a first clock input configured to receive a first clock signal, a second clock input configured to receive a second clock signal, and a mode input configured to receive the mode signal. The first and second clock signals are out of phase and have the same clock frequency. The clock generator () is configured to provide a generated clock signal whose effective frequency is based on the first and second clock signals and the mode signal.

Growing community of inventors

Austin, TX, United States of America

Atchyuth Gorti