Nxp B.v.

Cypress Semiconductor Corporation

Koninklijke Philips Corporation N.v.

Ata Khan

Gregory Goodhue

Harold Kutz

Hans Klein

Jean-Paul Vanitegem

Zhimin Ding

Pankaj Shrivastava

Eashwar Thiagarajan

Dennis Raymond Seguine

Mark E Hastings

Jaskarn Singh Johal

Carl Liepold

Kendall V Castor-Perry

Amsby D Richardson, Jr

Anasuya Pai Maroor

Greg Goodhue

John H Wharton

Haneef D Mohammed

Onur Ozbek

Robert Michael Kallal

Hans Van Antwerpen

Bruce E Byrkett

Craig A MacKenna

Rick Varney

Prithvi Nagaraj

Bas Van Der Veer

Kendall Castor-perry

Amsby Richardson

Jaskam Singh Johal

An integrated circuit (IC) device can include a plurality of analog blocks, including at least one fixed function analog circuit, a plurality of reconfigurable analog circuit blocks, at least one analog routing block reconfigurable to provide signal paths between any of the analog blocks; and a digital section comprising digital circuits; wherein each analog block includes dedicated of signal lines coupled to the at least one analog routing block.

Integrated circuit device with programmable analog subsystem

An integrated circuit (IC) device can include a plurality of analog blocks, including at least one fixed function analog circuit, and at least one reconfigurable analog circuit block selected from: a continuous time (CT) block comprising a plurality of reconfigurable amplifier circuits and a discrete time block comprising amplifiers with a reconfigurable switch network; an analog multiplexer (MUX) configured to selectively connect any of a plurality of input/outputs (I/Os) of the IC device to the analog blocks, the analog MUX including at least one low noise signal path pair having a lower resistance than other signal paths of the analog MUX; at least one analog routing block reconfigurable to provide signal paths between any of the analog blocks; a digital section comprising digital circuits; and a processor interface coupled to the analog blocks.

An integrated circuit device can include a plurality of analog blocks, including a plurality of programmable analog blocks configurable to provide different analog functions in response to configuration data, at least one programmable analog block including a programmable analog routing coupled to a plurality of external connections to the integrated circuit device; and a plurality of programmable digital blocks, at least one programmable digital block configurable into an analog block control circuit that configures the programmable analog routing.

Integrated circuit device with programmable blocks and analog circuit control

An integrated circuit device can include a plurality of analog blocks, at least a first analog block comprising a data converter circuit, each analog block including a programmable switch path coupled to a plurality of external connections to the integrated circuit device; and a plurality of programmable digital blocks, at least one programmable digital block configurable to control the programmable switch paths to couple external connections to the data converter circuit via an analog block other than the first analog block.

Aspects of the disclosure are directed to a system having a particularly-configured microcontroller. In one embodiment, the microcontroller includes the following: a processor; a processor data bus connected to the processor; a set of peripherals; a peripheral data bus connected to the peripherals; a peripheral bus bridge providing an interface between the processor data bus and the peripheral data base and including a plurality of special function register bank blocks that are internal to the microcontroller, each register bank block having a respective output; and a register bank block decoder circuit for decoding interrupts to provide a selection output for activation of one of the plurality of register bank blocks.

Microcontroller with an interrupt structure having programmable priority levels with each priority level associated with a different register set

A programmable processing device having a non-volatile memory that may comprise a first memory portion and a second memory portion, where the first section of the first memory portion is configured to store program instructions or data and the second memory portion of the memory word is configured to store either the configuration data or the error detection bits depending upon if an error detection scheme is implemented for the program instructions or data.

Using ECC memory to store configuration information

A microcontroller () includes a processor (), an embedded memory () operatively coupled to the processor (), and a microcontroller test interface () operatively connected to the processor () and the memory (). The microcontroller () responds to a reset signal to perform a reset initiation that causes an initial disabled state of the test interface () to be set and execution of initiation code with the processor (). This code execution optionally establishes a further disabled state. The microcontroller () provides an enabled state of the test interface for memory () access through the test interlace () during microcontroller () operation subsequent to the reset initiation unless the further disabled memory () access state is established by execution of the initiation code.

Controlling access to an embedded memory of a microcontroller

One embodiment of the present application includes a microcontroller () that has an embedded memory (), a programmable processor (), and a test interface (). The memory () is accessible through the test interface (). In response to resetting this microcontroller (), a counter is started and the test interface () is initially set to a disabled state while an initiation program is executed. The test interface () is changed to an enabled state&#x2014;such that access to the embedded memory () is permitted through it&#x2014;when the counter reaches a predefined value unless the microcontroller () executes programming code before the predefined value is reached to provide the disabled state during subsequent microcontroller () operation.

Embedded memory protection

One embodiment of the present invention is a microcontroller () including an embedded memory (), waveform control circuitry () operatively coupled to the memory (), several terminals (), and a programmable processor (). Processor () is responsive to execution of the first sequence of instructions to store a waveform bit pattern in memory () with a desired transmission timing. Waveform circuitry () is responsive to processor () to control transmission of the waveform bit pattern stored in memory () through one or more of the terminals () in accordance with the timing while processor () executes the second sequence of instructions to perform a different process.

Microcontroller waveform generation

All pointer-based accesses require first that the value contained in a pointer register to be read and then that value be used as an address to the appropriate region in random access memory (RAM). As implemented today, this requires two memory read access cycles, each of which takes at least one clock cycle and therefore this implementation does not allow single cycle operation. In accordance with an embodiment of the invention, when an access is performed to pointer memory to read the contents of a pointer, it is the shadow memory that is actually read and that returns the pointer value. Since the shadow memory is made up of pointer registers, a read access involves multiplexing out of appropriate data for the pointer address from these pointer registers to form a target pointer address. This target pointer address is then used as an address to access RAM without the overhead of a clock, since the register access is purely combinatorial and does not require clock-phase related timing as does access to the RAM.

Memory organization allowing single cycle pointer addressing where the address of the pointer is also contained in one of the memory locations

A memory accelerator module buffers program instructions and/or data for high speed access using a deterministic access protocol. The program memory is logically partitioned into 'stripes', or 'cyclically sequential' partitions, and the memory accelerator module includes a latch that is associated with each partition. When a particular partition is accessed, it is loaded into its corresponding latch, and the instructions in the next sequential partition are automatically pre-fetched into their corresponding latch. In this manner, the performance of a sequential-access process will have a known response, because the pre-fetched instructions from the next partition will be in the latch when the program sequences to these instructions. Previously accessed blocks remain in their corresponding latches until the pre-fetch process &#x2018;cycles around&#x2019; and overwrites the contents of each sequentially-accessed latch. In this manner, the performance of a loop process, with regard to memory access, will be determined based solely on the size of the loop. If the loop is below a given size, it will be executable without overwriting existing latches, and therefore will not incur memory access delays as it repeatedly executes instructions contained within the latches. If the loop is above a given size, it will overwrite existing latches containing portions of the loop, and therefore require subsequent re-loadings of the latch with each loop. Because the pre-fetch is automatic, and determined solely on the currently accessed instruction, the complexity and overhead associated with this memory acceleration is minimal.

Memory accelerator with two instruction set fetch path to prefetch second set while executing first set of number of instructions in access delay to instruction cycle ratio

A memory accelerator module buffers program instructions and/or data for high speed access using a deterministic access protocol. The program memory is logically partitioned into 'stripes', or 'cyclically sequential' partitions, and the memory accelerator module includes a latch that is associated with each partition. When a particular partition is accessed, it is loaded into its corresponding latch, and the instructions in the next sequential partition are automatically pre-fetched into their corresponding latch. In this manner, the performance of a sequential-access process will have a known response, because the pre-fetched instructions from the next partition will be in the latch when the program sequences to these instructions. Previously accessed blocks remain in their corresponding latches until the pre-fetch process &lsquo;cycles around&rsquo; and overwrites the contents of each sequentially-accessed latch. In this manner, the performance of a loop process, with regard to memory access, will be determined based solely on the size of the loop. If the loop is below a given size, it will be executable without overwriting existing latches, and therefore will not incur memory access delays as it repeatedly executes instructions contained within the latches. If the loop is above a given size, it will overwrite existing latches containing portions of the loop, and therefore require subsequent re-loadings of the latch with each loop. Because the pre-fetch is automatic, and determined solely on the currently accessed instruction, the complexity and overhead associated with this memory acceleration is minimal.

Memory accelerator for ARM processor pre-fetching multiple instructions from cyclically sequential memory partitions

A processing system supports memory access based on distinct memory space access instructions as well as universal access instructions that are independent of memory space partitions. Conventional memory-space dependent instructions, such as MOV, MOVX, and MOVC, provide an optimized addressing scheme, and an extended memory-space independent instruction EMOV provides an optimized code efficiency, processing speed, and ease of code generation. A mapping between the discrete memory space partitions and a &ldquo;universal&rdquo; memory space allocation is provided. The processing hardware interprets the universal address to determine the corresponding memory space, and provides the access to an address within that memory space.

Universal pointer implementation scheme for uniformly addressing distinct memory spaces in a processor's address space

A memory access architecture and technique employs multiple independent buffers that are configured to store items from memory sequentially. The memory is logically partitioned, and each independent buffer is associated with a corresponding memory partition. The partitioning is cyclically sequential, based on the total number of buffers, K, and the size of the buffers, N. The first N memory locations are allocated to the first partition; the next N memory locations to the second partition; and so on until the K partition. The next N memory locations, after the K partition, are allocated to the first partition; the next N locations are allocated to the second partition; and so on. When an item is accessed from memory, the buffer corresponding to the item's memory location is loaded from memory, and a prefetch of the next sequential partition commences to load the next buffer. During program execution, the 'steady state' of the buffer contents corresponds to a buffer containing the current instruction, one or more buffers containing instructions immediately following the current instruction, and one or more buffers containing instructions immediately preceding the current instruction. This steady state condition is particularly well suited for executing program loops, or a continuous sequence of program instructions, and other common program structures. The parameters K and N are selected to accommodate typically sized program loops.

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Saratoga, CA, United States of America

Ata Khan