Micron Technology Incorporated

Other

Aswin Thiruvengadam

Daniel L Lowrance

Peter Sean Feeley

Daniel G Scobee

Aleksandr Semenuk

Sivagnanam Parthasarathy

William A Melton

Frederick Jensen

Vamsi Pavan Rayaprolu

Hernan Adolfo Castro

Richard Edward Fackenthal

Angelo Visconti

Rich Fackenthal

Mauro Bonanomi

Peter B Harrington

Joshua Phelps

Andrew Oen

Robert Minguez, Ii

Christian Roque

Ravidath Gurudath

Preston Allen Thomson

Nicholas T Hendrickson

The present disclosure includes apparatuses and methods related to determining trim settings on a memory device. An example apparatus can determine a set of trim settings for the array of memory cells based on the operational characteristics of the array of memory cells, wherein the set of trim settings are associated with desired operational characteristics for the array of memory cells.

Trim setting determination on a memory device

The present disclosure includes apparatuses and methods related to a memory system including a controller and an array of memory cells. An example apparatus can include a controller configured to receive operational characteristics of an array of memory cells based on prior operations performed by the array of memory cells, determine a set of trim settings for the array of memory cells based on the operational characteristics of the array of memory cells, wherein the set of trim settings are associated with desired operational characteristics for the array of memory cells, and send the set of trim settings to the array of memory cells.

Trim setting determination for a memory device

Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including running sample data through each of a set of error-handling operations performed on data residing in a segment of the memory device in an existing order; and determining an optimized order of the set of error-handling operations based on probability data and latency data, wherein the probability data is associated with a result of running the sample data, and wherein the optimized order comprises an adjustment to an order of one or more error-handling operations of the set of error-handling operations in the existing order.

Management of error-handling flows in memory devices using probability data structure

Methods, systems, and devices for a model for predicting memory system performance are described. A memory system may generate a set of read commands and perform a first set of read operations at a memory device according to the generated read commands. The memory system may generate information indicating a performance of the memory device based on the first set of read operations and may update one or more coefficients of a model that correlates the information with a change in a read window. In some cases, the memory system may model the change in a read window based on the information and update one or more parameters associated with read operations based on the modelled change in the read window. The memory system may perform a second set of read operations at the memory device using the one or more updated parameters.

Model for predicting memory system performance

An apparatus includes a first thermoelectric component (TEC), a second TEC, a thermal transfer component disposed between the first TEC and the second TEC and a thermal conduction layer. The thermal conduction layer is coupled to the second TEC. The thermal conduction layer includes a planar area configured to be positioned above two or more electronic devices of multiple electronic devices of an electronic system to transfer thermal energy at the two or more electronic devices based on the first TEC, the second TEC and the thermal transfer component.

Temperature control component for electronic systems wherein a thermal transfer component is tappered

Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including running sample data through each of a set of error-handling operations performed on data residing in a segment of the memory device in an existing order associated with a workload; obtaining error recovery data as a result of running the sample data; and determining an optimized order of the set of error-handling operations based on probability of error recovery and latency data, wherein the probability of error recovery is based on the error recovery data, and wherein the optimized order comprises an adjustment to an order of one or more error-handling operations of the set of error-handling operations in the existing order.

The present disclosure includes apparatuses and methods related to configurable trim settings on a memory device. An example apparatus can include configuring a set of trim settings for an array of memory cells such that the array of memory cells have desired operational characteristics in response to being operated with the set of trim settings.

Configurable trim settings on a memory device

The present disclosure includes apparatuses and methods related to selectable trim settings on a memory device. An example apparatus can store a number of sets of trim settings and select a particular set of trims settings of the number of sets of trim settings based on desired operational characteristics for the array of memory cells.

Selectable trim settings on a memory device

A system includes a memory component and a processing device, operatively coupled with the memory component, to receive a request to perform a first test of memory components at a test platform, identify test resources of the test platform that are associated with the memory components, identify, among the test resources, a subset of test resources that are not being used by a second test of the memory components at the test platform, and assign, based on the subset of the test resources, a test resource of the test resources to obtain an assigned test resource for use by the test.

Allocation of test resources to perform a test of memory components

A thermal chamber multiple sides that form an enclosed chamber. The thermal chamber includes a first side of the multiple sides, the first side configured to adjustably mount an electronic circuit board within the enclosed chamber. The thermal chamber includes a second side of the multiple sides, the second side located opposite the first side and including one or more ports that expose the enclosed chamber. Each of the one or more ports is configured to receive a temperature control component that transfers thermal energy locally to and from a plurality of electronic devices of an electronic system that is coupled to and positioned above the electronic circuit board.

Standalone thermal chamber for a temperature control component

Disclosed is a system comprising a memory component having a plurality of memory cells capable of being in a plurality of states, each state of the plurality of states corresponding to a value stored by the memory cell, and a processing device, operatively coupled with the memory component, to perform operations comprising: obtaining, for the plurality of memory cells, a plurality of distributions of threshold voltages, wherein each of the plurality of distributions corresponds to one of the plurality of states, classifying each of the plurality of distributions among one of a plurality of classes, generating a vector comprising a plurality of components, wherein each of the plurality of components represents the class of a respective one of the plurality of distributions, and processing, using a classifier, the generated vector to determine a likelihood that the memory component will fail within a target period of time.

Analysis of memory sub-systems based on threshold distributions

Thermal control component

A thermal chamber includes a cavity that is enclosed by sides and one or more ports that expose the cavity within the thermal chamber. Each of the one or more ports is configured to receive a temperature control component having a solid physical structure and configured to transfer thermal energy to and from an electrical device exposed via the cavity. The thermal chamber includes a bottom side open area of the thermal chamber located below the one or more ports. The bottom side open area is configured to allow the temperature control component to contact the electrical device that is exposed via the bottom side open area.

Growing community of inventors

Folsom, CA, United States of America

Aswin Thiruvengadam