Texas Instruments Corporation

Aswin Srinivasa Rao

Karthik Subburaj

Anand Devendra Kudari

Binary frequency shift keying modulation is implemented by choosing appropriate phases of a high frequency clock to generate a modulated intermediate clock frequency. The high frequency clock is chosen to be (M+0.5)*fc, where fc is the carrier frequency and M is an integer. Depending on the binary data '1' or '0' to be transmitted, &#x2018;M&#x2019; or &#x2018;M+1&#x2019; clock phases from the high frequency clock are converted to an intermediate clock that is 2*N times faster than the carrier frequency, where N is an integer. This intermediate clock, generated entirely in the digital domain, has the required data modulation in it, and is used to generate N pulse width modulated (PWM) phases of waveforms operating at the carrier frequency. The N phases are then weighed appropriately to synthesize a sine waveform whose lower harmonics are substantially suppressed.

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Aswin Srinivasa Rao