Intel Corporation

Aswin Ramachandran

Arvind Raman

Darren S Crews

Vasudev Bibikar

Moorthy Rajesh

Chin Seng Lu

A computing device, system and method. The computing device includes a memory storing instructions, and a processing circuitry coupled to the memory. The processing circuitry is configured to execute the instructions to process a first control signal and a second control signal from respective first and second control pins of a computing platform. The processing circuitry is further to transition the computing platform, based on a combination of the first control signal and the second control signal and using at least one voltage pin on the platform, between a low power state and a retention power state without transitioning to an operational power state in between.

Mechanism to enter or exit retention level voltage while a system-on-a-chip is in low power mode

Technologies of managing power during an activation cycle of a processor core or other compute domain include determining new operation limits for active processor cores or other compute domains during an activation cycle of a hibernating processor core or other hibernating compute domain to reduce the likelihood of a power surge during the activation of the hibernating processor core or other compute domain. The active processor cores or other compute domain are monitored until their operating points are at or below the new operating limits. Thereafter, the hibernating processor core or other hibernating compute domain is activated.

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Austin, TX, United States of America

Aswin Ramachandran