Intel Corporation

Aswin Padmanabhan

Sangeeta Ghangam Manepalli

Robert J Johnston

Todd M Witter

Satyeshwar Singh

Chandra Mohan Konduru

Karthik Tyamgondlu

Benjamin Thomas Cope

Kiran K Velicheti

In one embodiment, video content displayed across a plurality of display devices is synchronized by first obtaining a first set of VSYNC timestamps for a display controller of a first video display device and a second set of VSYNC timestamps for a display controller of a second video display device. An adjustment factor is determined based on a comparison of the first and second VSYNC timestamps, and an adjusted VSYNC period for the display controller of the second video display device is programmed based on the determined adjustment factor. After a predetermined number of VSYNC cycles, the display controller of the second video display device reverts back to an original VSYNC period.

Multi-display video synchronization

In one embodiment, a processing device includes a plurality of display interfaces, a plurality of display controllers, and display synchronization circuitry. The display interfaces are used to interface with a plurality of display devices, and the display controllers are used to output video frames to the display devices via the display interfaces. Moreover, the display synchronization circuitry includes a clock synchronization interface and a frame synchronization interface. The clock synchronization interface is used to synchronize a clock rate across the display controllers, while the frame synchronization interface is used to synchronize a frame rate across the display controllers.

Hardware architecture for multi-display video synchronization

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San Jose, CA, United States of America

Aswin Padmanabhan