Texas Instruments Corporation

Aswath Vs

Jaiganesh Balakrishnan

Sriram Murali

Sarma Sundareswara Gunturi

Sundarrajan Rangachari

Sreenath Narayanan Potty

Girish Nadiger

Sandeep Kesrimal Oswal

Jawaharlal Tangudu

Sthanunathan Ramakrishnan

Rahul Anand Sharma

Pankaj Gupta

Sashidharan Venkatraman

Nagalinga Swamy Basayya Aremallapur

Ajai Paulose

Sanjay Pennam

Prasad Gandewar

Divyansh Jain

Ankur Jain

Kapil Kumar

Raunak Dhaniwala

Crest factor reduction circuitry includes: a peak neighborhood analyzer; peak detection circuitry and a controller. The peak neighborhood analyzer is configured to: receive an input signal; analyze the input signal to determine whether a peak larger than a target threshold is expected within an interval; and provide a first control signal responsive to determining that a peak larger than the target threshold is expected within the interval. The controller is configured to: receive the first control signal; and gate a clock or data to the peak detection circuitry responsive to the first control signal.

Power efficient crest factor reduction

An example apparatus includes: nonlinearity function selection circuitry with an output, the nonlinearity function selection circuitry to select a type of a nonlinearity function, the nonlinearity function to model nonlinearity portions of data output from an analog-to-digital converter, nonlinearity function term generation circuitry with a first input coupled to the output, the nonlinearity function term generation circuitry to generate one or more nonlinearity function terms of the nonlinearity function based on the type of the nonlinearity function and the data, and coefficient determination circuitry with a second input coupled to the output, the coefficient determination circuitry to determine one or more nonlinearity function coefficients based on the one or more nonlinearity function terms, the nonlinearity portions of the data to be compensated based on the one or more nonlinearity function coefficients.

High order nonlinearity estimation of radiofrequency analog-to-digital converters

A digital down converter (DDC) that improves efficiency by taking advantage of the periodicity of the coarse mixing process and the memory inherent in the convolution operation performed by decimation filters. In embodiments, the DDC filters and decimates a received signal to generate subfilter outputs and coarse mixes the subfilter outputs for each frequency band of interest. Accordingly, the DDC eliminates the need for separate decimation filters for each of the in-phase (I-phase) and quadrature (Q-phase) signals of each frequency band. In some embodiments, for each frequency band, the DDC combines the subfilter outputs into partial sums for each of the I- and Q-phases. In some of those embodiments, the coarse mixing operation is performed by multiplying the partial sums by real multiplicands and performing a simple post-rotation operation. In those embodiments, the DDC significantly reduces the number of multiplication operations required to perform the coarse mixing process.

Filtered coarse mixer based digital down-converter for RF sampling ADCs

Analog gain correction circuitry and analog switching clock edge timing correction circuitry can provide coarse correction of interleaving errors in radio-frequency digital-to-analog converters (RF DACs), such as may be used in 5G wireless base stations. The analog correction can be supplemented by digital circuitry configured to 'pre-cancel' an interleaving image by adding to a digital DAC input signal a signal equal and opposite to an interleaving image created by the interleaving DAC, such that the interleaving image is effectively mitigated. Error correction control parameters can be periodically adjusted for changes in temperature by a controller coupled to an on-chip temperature sensor. A model useful for understanding the sources of error in interleaving DACs is also described.

Interleaving errors sources and their correction for RF DACs

One example includes a receiver system. The receiver system includes an analog-to-digital converter (ADC) configured to convert an analog input signal into a digital output signal at a sampling frequency. The receiver system also includes a spur correction system configured to receive the digital output signal and to estimate spurs associated with the digital output signal and to selectively correct a subset of the spurs associated with a set of frequencies that are based on the sampling frequency.

Spur estimating receiver system

A system for generating secondary clock signals from a primary clock signal includes a dithered clock divider which has a first input adapted to receive the primary clock signal and a second input adapted to receive a random division ratio. The dithered clock divider provides a dithered clock signal. The system includes a multi-phase clock generator which has a first input adapted to receive the primary clock signal, a second input adapted to receive the dithered clock signal, and a third input adapted to receive a pseudo-random pattern. The multi-phase clock generator provides the secondary clock signals from multiple phases of the dithered clock signal. The system includes a pseudo-random pattern generator which provides the pseudo-random pattern.

Methods and systems for generation of balanced secondary clocks from root clock

A digital local oscillator includes a look-up table and oscillator control circuitry. The look-up table contains samples of the digital local oscillator signal. The oscillator control circuitry is configured to select samples from the look-up table based on an accumulated phase value. The oscillator control circuitry is also configured to add a correction value to the accumulated phase value based on a difference of a frequency of the digital local oscillator signal and a desired frequency.

Digital downconverter with digital oscillator frequency error correction

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Kannur, India

Aswath Vs