Tower Semiconductor Ltd.

Trieye Ltd.

Hillberry Gat Ltd.

Assaf Lahav

Amos Fenigstein

Yakov Roizin

Avi Strum

David Cohen

Edward J Preisler

Clifford I Drowley

Vladimir Korobov

Omer Kapach

Uriel Levy

Avraham Bakal

Ira Naot

Shai Kfir

Anatoly Sergienko

Zohar Kuritsky

Viktor Goldovsky

David Avner

Omer Katz

Naor Inbar

Yohanan Davidovich

Dmitry Veinger

Ruthie Shima-Edelstein

Light detecting structures comprising germanium (Ge) photodiodes formed in a device layer of a germanium on-insulator (GeOI) wafer, focal planes arrays based on such Ge photodiodes (PDs) and methods for fabricating such Ge photodiodes and focal plane arrays (FPAs). An FPA includes a Ge-on-GeOI PD array bonded to a ROIC where the handle layer of the GeOI layer is removed. The GeOI insulator properties and thickness can be designed to improve light coupling into the PDs.

Germanium on insulator for CMOS imagers in the short wave infrared

An image sensor module that comprises a die, wherein the die comprises light sensors and optics; and wherein the optics comprises luminescent elements that represent die manufacturing information that is indicative of a manufacturing process of the die.

Image sensor module and a method for evaluating an image sensor

A backside illuminated semiconductor image sensor that includes a Fabry-Perot resonator tuned to absorb near infrared (NIR) radiation; wherein the Fabry-Perot resonator comprises a front reflector, a back reflector and an active Silicon layer between the front reflector and the back reflector.

Backside illuminated (BSI) CMOS image sensor (CIS) with a resonant cavity and a method for manufacturing the BSI CIS

A global shutter image sensor formed on an n-type bulk substrate and including pixels having pinned n-type photodiodes and memory nodes formed in designated n-doped epitaxial layer regions that are separated from the bulk substrate by a p-type vertical (potential) barrier implant. Each memory node includes both a buried channel portion and a contiguous pinned diode portion having different doping levels such that an intrinsic lateral electrical field drives electrons from the buried channel portion into the pinned diode portion during global charge transfer from an adjacent photodiode. The p-type vertical (potential) barrier implant is coupled to ground, and the bulk substrate is switched between a low integration voltage level during integration periods, and a high reset voltage level, whereby the photodiodes are globally reset without requiring reset transistors. P-type sinker implant sections and p-type vertical barrier implants form box-like diffusions around each pixel's photodiode and memory node.

Image sensor pixel with memory node having buried channel and diode portions formed on N-type substrate

A global shutter (GS) image sensor pixel includes a pinned photodiode connected to a memory node by a first transfer gate transistor, and a floating diffusion connected to the memory node by a second transfer gate transistor. The memory node includes a buried channel portion disposed under the first transfer gate transistor and a contiguous pinned diode portion disposed between the first and second transfer gate transistors, where the two memory node portions have different doping levels such that an intrinsic lateral electrical field drives electrons from the buried channel portion into the pinned diode portion. The floating diffusion node similarly includes a buried channel portion disposed under the second transfer gate transistor and a contiguous pinned diode portion that generate a second intrinsic lateral electrical field that drives electrons into the pinned diode portion of the floating diffusion. A 6T CMOS pixel is disclosed that facilitates low-noise CDS readout.

Image sensor pixel with memory node having buried channel and diode portions

Some demonstrative embodiments include devices and/or methods of Back Side Illumination (BSI) Complementary Metal-Oxide-Semiconductor (CMOS) pixel array. For example, a BSI CMOS pixel array may include a plurality of pixels, a pixel of the plurality of pixels may include one or more Metal-Oxide-Semiconductor (MOS) transistors comprising one or more well regions, a well region of the one or more well regions comprising an N-Well (NW) region or a P-well (PW) region; a photodiode; an epitaxial (epi) layer comprising an absorption area and a collection area, the absorption area to absorb incoming photons and to generate electrons responsive to absorbed photons, and the collection area connecting the absorption area to the photodiode to provide the electrons from the absorption area to the photodiode; and a barrier layer separating the absorption area from the one or more well regions.

Apparatus, system and method of back side illumination (BSI) complementary metal-oxide-semiconductor (CMOS) pixel array

Some demonstrative embodiments include devices and/or methods of gettering on silicon on insulator (SOI) substrate. For example, a complementary metal-oxide-semiconductor (CMOS) integrated circuit (IC) may include a plurality of pixels arranged on a wafer, a pixel of the pixels including: a silicon active area; at least one non-silicided leakage-sensitive component formed on the active area, the leakage-sensitive component is sensitive to metal contaminants; a non-leakage-sensitive area formed on the active area, the non-leakage-sensitive area surrounding the leakage-sensitive component; and at least one silicided gettering region formed on the non-leakage-sensitive area to trap the metal contaminants.

Device and method of gettering on silicon on insulator (SOI) substrate

A method for operating a global shutter image sensor includes performing both a global shutter (image capture) operation and a rolling shutter (readout) operation. During the global shutter operation, image information (charges) are captured by photodiodes in every pixel, and then simultaneously transferred to charge coupled gate (CCG) devices provided in each pixel. The rolling shutter operation includes performing multiple correlated double sampling (CDS) readout phases utilizing readout circuits that are shared by groups of pixels (e.g., four pixels share each readout circuit) having CCG devices connected in a chain. After resetting a floating diffusion in the readout circuit, a first captured charge is transferred to floating diffusion for readout, and the remaining charges are shifted along the CCG chain. The remaining CCG devices are then sequentially read out by repeating the read-and-shift operation. The readout operation is then repeated for each row of pixel groups.

Shared readout low noise global shutter image sensor method

A global shutter image sensor includes an array of pixel groups arranged in rows and columns, each pixel group including four pixels and a shared readout circuit having a floating diffusion. Each pixel includes a photodiode, a transfer gate and a charge coupled gate (CCG) device. The CCG devices are coupled in series with the floating diffusion of the shared readout circuit. Control circuitry controls the image sensor such that all of the pixels simultaneously capture image information (charges) and then transfer the captured charges to the CCG devices during a global shutter operation. The control circuit then controls the CCG devices to act as a shift register that transfers the captured charges to the floating diffusion during sequential correlated double sampling readout phases. The readout circuit includes a shared reset transistor, a source-follower and row select transistor, and each pixel group is controlled by eight or fewer control signals.

Shared readout low noise global shutter image sensor

A CMOS image sensor uses a special exposure control circuit to independently adjust the photodiode exposure (integration) time for each pixel in a pixel array to obtain non-saturated photodiode charges for each pixel. Exposure time adjustment involves extrapolating a pixel's final photodiode charge using an intermediate photodiode charge measured after a predetermined portion of an exposure frame period. If the intermediate photodiode charge is, e.g., over 50% of the photodiode's full-well capacity after half of the exposure frame period, then saturation is likely and the photodiode is reset to integrate only during the remaining time. If not, then the photodiode integrates over the allotted exposure frame period. Data indicating the length of the exposure portion is stored as analog data on the memory node of each pixel, and readout of the final photodiode charge is performed using Correlated Double Sampling (CDS) techniques.

CMOS image sensor with wide (intra-scene) dynamic range

A CMOS image sensor in which each pixel includes a conventional pinned diode (photodiode), a Wide Dynamic Range (WDR) detection (e.g., a simplified time-to-saturation (TTS)) circuit, a correlated double sampling (CDS) circuit, and a single output chain that is shared by both the CDS and WDR circuits. The pinned diode is used in the conversion of photons into charge in each pixel. In one embodiment, light received by the photodiode is processed using a TTS operation during the CDS integration phase, and the resulting TTS output signal is used to determine whether the photodiode is saturated. When the photodiode is saturated, the TTS output signal is processed to determine the amount of light received by the photodiode. When the photodiode is not saturated, the amount of light received by the photodiode is determined using signals generated by the readout phase of the CDS operation.

CMOS image sensor with high sensitivity wide dynamic range pixel for high resolution applications

A color image sensor includes an array of pixels arranged in a plurality of pixel groups, each pixel group including a floating diffusion that is shared by four pixels disposed in a 2&#xd7;2 arrangement. Each of said four pixels includes a photodetector and a color filter superposed over the photodetector, wherein a first pair of said four pixels include green color, and a second pair of said four pixels includes either red or blue color filters. A control circuit controls the pixel groups such that discrete image information is generated from each pixel in normal light situations, and such that summed image information is generated from each pixel group in low light situations by simultaneously connecting the green pixels to the floating diffusion during a first time period, and simultaneously connecting the red/blue pixels to said floating diffusion during a second time period.

Color pattern and pixel level binning for APS image sensor using 2&#xd7;2 photodiode sharing scheme

A capacitor for a single-poly floating gate device is fabricated on a semiconductor substrate along with low and high voltage transistors. Each transistor has a gate width greater than or equal to a minimum gate width of the associated process. A dielectric layer is formed over the substrate, and a patterned polysilicon structure is formed over the dielectric layer. The patterned polysilicon structure includes one or more narrow polysilicon lines, each having a width less than the minimum gate width. The LDD implants for low and high voltage transistors of the same conductivity type are allowed to enter the substrate, using the patterned polysilicon structure as a mask. A thermal drive-in cycle results in a continuous diffusion region that merges under the narrow polysilicon lines. Contacts formed adjacent to the narrow polysilicon lines and a metal-1 trace connected to the contacts may increase the resulting capacitance.

Method for fabricating three-dimensional control-gate architecture for single poly EPROM memory devices in planar CMOS technology

A CMOS image sensor includes a pinned photodiode and a transfer gate that are formed using a thick mask that is self-aligned to at least one edge of the polysilicon gate structure to facilitate both the formation of a deep implant and to provide proper alignment between the photodiode implant and the gate. In one embodiment a drain side implant is formed concurrently with the deep n-type implant of the photodiode. After the deep implant, the mask is removed and a shallow p+ implant is formed to complete the photodiode. In another embodiment, the polysilicon is etched to define only a drain side edge, a shallow drain side implant is performed, and then a thick mask is provided and used to complete the gate structure, and is retained during the subsequent high energy implant. Alternatively, the high energy implant is performed prior to the shallow drain side implant.

Growing community of inventors

Binyamina, Israel

Assaf Lahav