Intel Corporation

Assaf Benhamou

Adee Ofir Ran

Yoni Landau

Amir Mezer

Mark A Bordogna

Ehud Udi Shoor

Janardhan H Satyanarayana

Itamar Fredi Levin

Amir Laufer

Dror Lazar

Kevan A Lillie

Alon Meisler

Itay Tamir

Shlomi Lalush

Yaakov Dalsace

Michael J Hill

Todd W Mellinger

Srikrishnan Venkataraman

Yaniv Hadar

Harry Birenboim

David Golodni

Ahmed Fouad Salama

Paul K Tucker

Techniques and apparatus to provide for interactions between system components are described. In one embodiment, an apparatus to provide a component interface, the apparatus comprising at least one memory, a first component comprising at least one register, logic, at least a portion of comprised in hardware, the logic to define at least one interface field stored in the at least one register, generate an interface with a second component based on the at least one interface field, and receive interface information from the second component via the interface, the interface information comprising at least one value for the at least one interface field.

Component firmware interaction using hardware registers

Technologies for timestamping data packets with forward error correction is disclosed. Alignment markers may be inserted in a data stream in order to assist with synchronization on the receiving end. After insertion of the alignment markers, a start of frame delimiter or other trigger may be detected, triggering a timestamp corresponding to the start of frame delimiter or other trigger. The data and the timestamp are sent to a remote compute device, which may timestamp the data before removing the alignment markers. With this approach, insertion of the alignment markers does not lead to a deviation in the timestamp of the sending compute device or the receiving compute device.

Technologies for timestamping with error correction

Computing devices and techniques for providing link partner health reporting are described. In one embodiment, for example, an apparatus may include at least one memory, and logic, at least a portion of the logic comprised in hardware coupled to the at least one memory, the logic to determine a plurality of error counters, each of the plurality of error counters associated with a number of errors, determine the number of errors for each data unit of a plurality of data units associated with a data block, increment each of the plurality of error counters corresponding with the number of errors for each data unit of the plurality of data units, provide a plurality of error counts for the data block to a link partner, the plurality of error counts corresponding to the number of errors accumulated in each of the plurality of error counters for the data block, and reset the plurality of error counters. Other embodiments are described and claimed.

Techniques for link partner error reporting

An apparatus system is provided which comprises: a first component to receive a first signal via a first delay circuit; a second component to receive a second signal via a second delay circuit; and one or more circuitries to tune a first delay of the first delay circuit and a second delay of the second delay circuit, based at least in part on monitoring of a voltage level.

Tunable delay control of a power delivery network

Technologies for robust data transmission include a network port logic having a physical coding sublayer (PCS). The PCS may transmit a series of rapid alignment markers (RAMs) to a link partner, with each RAM indicative of a counter value. The PCS transitions to a sleep state if the counter value equals two and a low power idle (LPI) command is set by an upper-layer client. The PCS transitions to an active state if the counter value equals one and the LPI command is not set. The PCS may receive a low power idle symbol (LI) from the link partner and start a guard timer in response to receipt of the LI symbol. The PCS transitions to a sleep state if the guard timer expires and transitions to the active state if data other than LI is received prior to expiration of the guard timer. Other embodiments are described and claimed.

Technologies for ethernet link robustness for deep sleep low power applications

In one embodiment, the present invention includes a de-serializer to receive serial data at a first rate and to output a parallel data frame corresponding to the serial data aligned to a frame alignment boundary in response to a phase control signal received from a feedback loop coupled between the de-serializer and a receiver logic coupled to an output of the de-serializer. Other embodiments are described and claimed.

Providing a feedback loop in a low latency serial interconnect architecture

A device, comprising a monitoring slicer adapted to repeatedly sample an internal analog signal to provide a sequence of digital outputs indicating a result of a comparison of the level of the internal analog signal to a reference voltage and an operative unit adapted to perform a task of the device and provide a result without using digital outputs from the monitoring slicer.

Probing analog signals

In one embodiment, the present invention includes an apparatus having an automatic gain control (AGC) stage to receive an input signal from a communication channel physical medium, a first local gain stage coupled to an output of the AGC stage, an equalizer coupled to an output of the first local gain stage, an echo canceller to receive local data to be transmitted along the communication channel physical medium, and a second local gain stage coupled to an output of the echo canceller. Other embodiments are described and claimed.

Maintaining convergence of a receiver during changing conditions

Growing community of inventors

Haifa, Israel

Assaf Benhamou