Arm Limited

Åsmund Kvam Oma

Edvard Fielding

Antonio Garcia Guirado

Khaled Tarek Abdellatif Mohamed Khatib

A texture cache comprises at least two banks of cache storage to cache texels for processing in texture mapping operations. Access to the cached texels corresponding to a given chunk of texels of a given texture image is controlled according to a selected bank mapping selected from two or more bank mappings supported by the texture cache access control circuitry. Each bank mapping corresponds to a different mapping of the respective texels within the given chunk to the banks of cache storage. In at least one operating mode, the selected bank mapping is selected for the given chunk of texels of the given texture image depending on: at least one of first/second chunk position coordinates associated with the given chunk of texels; and at least one further texture attribute associated with the given texture image.

Texture mapping

A cache is disclosed in which a dedicated cache portion comprising one or more extra lines dedicated for data of a particular data type is provided alongside a shared cache portion. So long as there is a cache line available in the shared cache portion, data can be written into the shared cache portion. However, when the shared cache portion is fully locked such that no new data can be written into the shared cache portion, data can instead be written to its respective dedicated cache portion, effectively bypassing the fully locked shared cache portion.

Growing community of inventors

Trondheim, Norway

Åsmund Kvam Oma