Silicon Laboratories Inc.

Aslam A Rafi

Donald A Kerth

Thomas Saroshan David

Daniel J Cooley

An interface between two devices is disclosed. To consume power, the signals used in the interface utilize CMOS signalling. Further, to achieve high speed, a reduced frequency clock is transmitted from one device to the second device. The second device has a clock multiplier to recreate the original clock. Both devices utilize a clock phase alignment block which aligns the phase of the clock with the incoming data. The clock phase alignment block utilizes a digital PLL to consume power. Further, since the digital PLL retains its state, the reduced frequency clock may be disabled when data is not being transmitted. This interface may be used to transmit serial data at rates up to and exceeding 2.5 Gbits/sec.

Interface between processing unit and an external nonvolatile memory

A wireless communication device is disclosed wherein the voltage swing of a local oscillator (LO) signal is controlled to prevent overstressing semiconductor devices in a mixer to which the LO signal is supplied. A quadrature divider supplies the LO signal to the mixer. Digital calibration methodology controls the current that the quadrature divider draws from a power supply to set the voltage swing of the LO signal that the quadrature divider generates.

Wireless communication system and method using digital calibration to control mixer input swing

In one embodiment, a local oscillator and mixer architecture may include a frequency divider having I and Q channel master storage elements formed of devices of a first size, and I and Q channel slave storage elements formed of devices of a second size, where the second size is smaller than the first size. In such manner, power consumption may be reduced while reducing phase noise in signals provided from the frequency divider to the corresponding mixer.

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Austin, TX, United States of America

Aslam A Rafi