Texas Instruments Corporation

Analog Devices International Unlimited Company

Asit Shankar

Lars Risbo

Klaus Krogsgaard

Lieyi Fang

Josey George Angilivelil

An amplifier circuit can be configured to receive a differential input signal having a common mode component that can extend to at least one power supply rail for the amplifier circuit. The amplifier circuit can include an input stage, such as having a first differential transistor pair, and the input stage can receive the differential input signal and in response conduct a differential first current to a cascode output stage. The cascode output stage can include or use a cascode control signal that is adjusted in response to the differential input signal. The cascode control signal can be independent of a transconductance of the first differential transistor pair. In an example, the amplifier circuit includes a slew boost circuit configured to source or sink current at an output of the amplifier based on a magnitude and polarity of the differential input signal.

Amplifier with reduced power consumption and improved slew rate

A closed loop amplifier system comprising a modulator that provides a pulse-width modulated (PWM) output signal based on an input signal, the modulator having a variable closed loop transfer function. The system also comprises a ramp generator that provides a ramp signal to the modulator, the variable closed loop transfer function of the modulator varying as a function of the ramp signal. The system further comprises a controller that controls the ramp generator to provide the ramp signal to adjust the variable closed loop transfer function during transitions between operating states of the amplifier system.

Method and system for transitioning between operation states in an output system

A digital audio system including a digital phase-locked-loop circuit for generating a pulse-width-modulation (PWM) clock signal, applied to a pulse-code-modulation to pulse-width-modulation converter, is disclosed. The digital phase-locked loop includes a phase detector for measuring phase error between a reference signal and a feedback signal. A digital version of the phase error, after filtering by a loop filter, is converted to a digital delay control word that is sampled at twice its frequency. Successive samples of the delay control word control the propagation delay of first and second delay cells in an oscillator. The use of successive samples at substantially twice the frequency of change of the delay control word effectively realizes the sum of a sinc filter and a comb filter, which greatly suppresses the effects of jitter in the reference signal to the digital phase-locked loop.

All-digital phase-locked loop for a digital pulse-width modulator

The present invention achieves technical advantages as a high performance analog charge pumped phase locked loop (PLL)() with process and temperature compensation in closed loop bandwidth. The PLL reduces the variation in bandwidth and stability by making the product K*Iindependent of process and temperature variation. The PLL achieves a higher performance than existing PLL architectures, achieving a high dynamic range up to at least 110 dB, such that a PWM class-D amplifier is realizable with this PLL. The PLL has a constant bandwidth and damping factor while using an analog charge pump ().

Growing community of inventors

Murphy, TX, United States of America

Asit Shankar