Intel Corporation

Asit K Mishra

Robert Valentine

Elmoustapha Ould-Ahmed-Vall

Prasoonkumar Surti

Deborah T Marr

Edward Thomas Grochowski

Mark Jay Charney

Eriko Nurvitadhi

Simon C Steely, Jr

Gilbert A Neiger

Jesus Corbal

Rajesh M Sankaran

Koichi Yamada

Thomas D Fletcher

Joseph Nuzman

Dennis Ryan Bradford

Lokpraveen B Mosur

Paul Caprioli

Kshitij Arun Doshi

Amit Bleiweiss

Christopher J Hughes

Milind Baburao Girkar

Srikanth T Srinivasan

Wei W Wang

Alexander F Heinecke

Ehud Cohen

David Stewart Dunning

Nadathur Rajagopalan Satish

Wei D Wang

Dan Baum

Stephen R Van Doren

Wei Wang

Jong Soo Park

Howard S David

Jeffrey J Cook

Jonathan D Pearce

David B Sheffield

Narayan Ranganathan

Kent D Glossop

Niall D McDonnell

Richard J Greco

Ganesh Venkatesh

Dwight P Manley

Tracy Garrett Drysdale

Nicholas P Carter

Michael A O'Hanlon

Srinivas Sridharan

Dheevatsa Mudigere

Dhawal Srivastava

Mohammad Ashraf Bhuiyan

Anavai Ramesh

Md Faijul Amin

Niharika Maheshwari

Jesus Corbal San Adrian

Abhijit Davare

Andrey Ayupov

Anton Alexandrovich Sorokin

Steven Burns

Sheng C Li

Mikhail Smelyanskiy

Jianping Xu

Joshua B Fryman

Ronen Zohar

Desmond A Kirkpatrick

Debbie Marr

Michael A Anderson

Narayanan Sundaram

Mostofa Ali Patwary

Ould-Ahmed-Vall Elmoustapha

Niall D Mcdonnell

Michael A O'HANLON

An apparatus to facilitate acceleration of machine learning operations is disclosed. The apparatus comprises at least one processor to perform operations to implement a neural network and accelerator logic to perform communicatively coupled to the processor to perform compute operations for the neural network.

Machine learning accelerator mechanism

A processor of an aspect includes a decode unit to decode a matrix multiplication instruction. The matrix multiplication instruction is to indicate a first memory location of a first source matrix, is to indicate a second memory location of a second source matrix, and is to indicate a third memory location where a result matrix is to be stored. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the matrix multiplication instruction, is to multiply a portion of the first and second source matrices prior to an interruption, and store a completion progress indicator in response to the interruption. The completion progress indicator to indicate an amount of progress in multiplying the first and second source matrices, and storing corresponding result data to the third memory location, that is to have been completed prior to the interruption.

Interruptible and restartable matrix multiplication instructions, processors, methods, and systems

Embodiments of systems, methods, and apparatuses for heterogeneous computing are described. In some embodiments, a hardware heterogeneous scheduler dispatches instructions for execution on one or more plurality of heterogeneous processing elements, the instructions corresponding to a code fragment to be processed by the one or more of the plurality of heterogeneous processing elements, wherein the instructions are native instructions to at least one of the one or more of the plurality of heterogeneous processing elements.

Systems, methods, and apparatuses for heterogeneous computing

An apparatus and method for performing efficient, adaptable tensor operations. For example, one embodiment of a processor comprises: front end circuitry to schedule matrix operations responsive to a matrix multiplication instruction; a plurality of lanes to perform parallel execution of the matrix operations, wherein a lane comprises an arithmetic logic unit to multiply a block of a first matrix with a block of a second matrix to generate a product and to accumulate the product with a block of a third matrix, and wherein the matrix blocks are to be stored in registers within the lane; and broadcast circuitry to broadcast one or more invariant matrix blocks to at least one of different registers within the lane and different registers across different lanes.

Apparatus and method for adaptable and efficient lane-wise tensor processing

A processor includes a decode unit to decode an instruction that is to indicate a first source packed data operand that is to include at least four data elements, to indicate a second source packed data operand that is to include at least four data elements, and to indicate one or more destination storage locations. The execution unit, in response to the instruction, is to store at least one result mask operand in the destination storage location(s). The at least one result mask operand is to include a different mask element for each corresponding data element in one of the first and second source packed data operands in a same relative position. Each mask element is to indicate whether the corresponding data element in said one of the source packed data operands equals any of the data elements in the other of the source packed data operands.

Data element comparison processors, methods, systems, and instructions

An apparatus and method for performing efficient, adaptable tensor operations. For example, one embodiment of a processor comprises: front end circuitry to schedule a plurality of matrix operations responsive to a tensor matrix multiplication instruction; a plurality of lanes to perform parallel execution of the matrix operations, each lane comprising: first, second, and third tile registers to store blocks of a first matrix (A), second matrix (B), and third matrix (C), respectively; at least one tensor arithmetic logic unit (TALU) to multiply a block of elements of the first matrix with a block of elements of the second matrix to generate a product and to accumulate the product with a block of elements of the third matrix, wherein each lane is to multiply one or more different blocks of the first and second matrix and to accumulate the resulting one or more products with one or more different blocks of the third matrix; and broadcast circuitry to broadcast one or more invariant matrix blocks to different tile registers within a lane and/or different tile registers across different lanes.

A processor comprises a first register to store a plurality of data items at a plurality of positions within the first register, a second register, and an execution unit, operatively coupled to the first register and the second register, the execution unit comprising a logic circuit implementing a sort instruction for sorting the plurality of data items stored in the first register in an order of data item values, and storing, in the second register, a plurality of indices, wherein each index identifies a position associated with a data item stored in the first register prior to the sorting.

Byte and nibble sort instructions that produce sorted destination register and destination index mapping

Growing community of inventors

Hillsboro, OR, United States of America

Asit K Mishra