Advanced Micro Devices Corporation

Asim A Selcuk

Raymond T Lee

Stephen C Horne

John Christian Holst

Nicholas John Kepler

Christopher A Spence

Richard K Klein

Craig S Sander

Darrell M Erb

Rich K Klein

Christoper A Spence

Todd P Lukanc

Emi Ishida

Ming Yin Hao

Richard P Rouse

Pau-ling Chen

A method for fabricating a field effect transistor (FET) in and on a semiconductor substrate with local interconnects to permit the formation of minimal space between gate and the local interconnects by fabricating the source and drain of the FET and the local interconnects prior to forming the gate of the FET.

Minimizing transistor size in integrated circuits

Silicon-based, submicron-dimensioned MOS and/or CMOS transistor devices having substantially reduced source/drain junction-to-semiconductor substrate capacitance are formed by implanting oxygen atoms and/or molecules just below source/drain implant regions. Implantation conditions are selected to provide a peak oxygen implant concentration at a depth just below the ultimate source/drain junction depth. Subsequent thermal processing at elevated temperature results in source/drain dopant diffusion/activation and formation of a silicon oxide barrier layer or stratum just below the ultimate source/drain junction depth, thereby substantially reducing junction-to-substrate capacitance of refractory metal silicide-contact devices.

Oxygen implantation for reduction of junction capacitance in MOS transistors

An electrical alignment test structure is provided that enables accurate in-process alignment measurements. Embodiments include forming two conductive layers whose alignment is be tested on the surface of a semiconductor substrate, one layer having a generally trapezoidal &ldquo;shorting bar&rdquo; with symmetrically stepped sides, and the other layer having a snake-like resistor &ldquo;sladder&rdquo; with two symmetrical sets of rung-like segments, whose ends correspond to the steps of the sides of the shorting bar. The ladder and the shorting bar are disposed with the shorting bar between the two sets of segments of the ladder, such that when the two layers are formed properly aligned, an equal number of segments of each set of segments of the ladder makes contact with the shorting bar. Thus, when the two layers are properly aligned, the resistance of each of the two sets of segments of the ladder is about the same. However, when the layers are out of alignment more than a predetermined amount (i.e., the depth of a step of the shorting bar), a different number of segments short to the respective sides of the shorting bar, resulting in each set of segments having a different resistance measured at their ends. Since the resistance of each segment is significant (e.g., over 100 ohms), the resistance difference and, hence, the number of shorted segments on each side can be accurately calculated. Then, knowing the spacing of each step of the shorting bar, the alignment offset of the two layers can be calculated. Furthermore, by comparing the drawn separation of the ladder and the shorting bar with the calculated separation of these components of the actual test structure, quick and accurate measurement of critical dimension (CD) variation is provided.

Electrical alignment test structure using local interconnect ladder resistor

A device and method to modulate a gate polysilicon doping profile by performing a sidewall implantation. The method includes forming a gate on a substrate and implanting ions through a sidewall in the gate. The ion implantation is performed by projecting the ions at an angle that is not perpendicular to the top surface of substrate and in a direction that is towards the surface of sidewall. The ion implantation process can be performed using a type of dopant that either increases or decreases the net dopant concentration in a gate polysilicon layer in a region of the gate adjacent the sidewall and adjacent a gate oxide layer.

Modulation of gate polysilicon doping profile by sidewall implantation

A device and method for reducing parasitic capacitance between the gate and an adjacent conductive layer. A gate structure is provided having a polysilicon layer with recessed side portions. Sidewalls or spacers partially cover the sides of the polysilicon layer, while the exposed side portions of the polysilicon layer are etched to form the recessed side portions. The area that is etched away to form the recessed side portions accounts for the reduction in intra-level parasitic capacitance between the gate and adjacent conductive layers, such as local interconnect layers, interconnect layers, and contact layers. By removing the area etched away to form the recessed side portions, the separation between the gate and the conductive layer is increased, thereby inhibiting parasitic capacitance which, among other factors, is a function of the distance between two electrical components. Consequently, the present invention provides a simple device and method of reducing the parasitic capacitance of the semiconductor device without sacrificing valuable semiconductor space.

Gate structure having polysilicon layer with recessed side portions

A method of asymmetrically doping a region beneath a gate by controlling the lateral surface profile of the gate using a mask. A first embodiment of the method includes forming a mask over the gate such that it extends beyond the opposing sides of the gate in an uneven manner. A second embodiment of the method includes forming a mask including sidewall spacers on both sides of the gate in an uneven manner. The uneven manner of providing the mask for ion implantation can be used to define an asymmetric lateral channel profile, which can be advantageously used to vary gate overlap, channel V,, or source/drain doping as necessary.

Method of asymmetrically doping a region beneath a gate

A method of forming minimal gaps or spaces in conductive lines pattern for increasing the density of integrated circuits by first forming an opening in an insulating layer overlying the conductive line by conventional optical lithography, followed by forming sidewalls in the opening to create a reduced opening, and using the sidewalls as a mask to remove, preferably by etching, a portion of the conductive line pattern substantially equal in size to the reduced opening.

Forming minimal size spaces in integrated circuit conductive lines

A device and method to reduce resistance in polysilicon gates by forming a highly conductive plug within a trench in the gate. This is achieved by etching a trench between nitride sidewalls and into the polysilicon layer and depositing a metal (e.g. tungsten) plug therein. Certain embodiments include a gate structure positioned on a silicon substrate and a gate oxide layer positioned on the silicon substrate, a polysilicon layer positioned on the gate oxide layer, a nitride layer, which includes nitride sidewalls, positioned on the polysilicon layer, and a tungsten plug that is positioned within a first trench portion between the nitride sidewalls and a second trench portion in the polysilicon layer.

Polysilicon gate having a metal plug, for reduced gate resistance,

A method for fabricating a field effect transistor (FET) in and on a semiconductor substrate with local interconnects to permit the formation of minimal insulating space between polysilicon gate and the local interconnects by fabricating the source and drain of the FET and the local interconnects prior to forming the gate of the FET. A portion of an insulating layer between the source and drain is removed prior to forming the gate. Preferably, an etch stop layer on the semiconductor substrate underlying the insulating layer is used in the method.

A static random access memory (SRAM) cell having increased cell capacitance at the storage nodes utilizes a capacitive structure disposed in a trench. The capacitive structure includes an oxide liner disposed underneath two polysilicon plates. The polysilicon plates are each connected to drains of lateral transistors associated with the SRAM cell. The capacitive plates are deposited as a conformal layer polysilicon and then anisotropically etched to form plates on the side walls of the trench. A dielectric material such as silicon dioxide may be deposited between the polysilicon plates in the trench. The capacitor structures are provided between first and second N-channel pull down transistors associated with the SRAM cell.

Static random access memory cell having buried sidewall capacitors

A method and the resulting device to permit the formation of minimal insulating space between polysilicon gates by forming an insulating layer over the polysilicon gates and protecting selected ones of the gates and the insulating layer with an etch barrier so that the opening for local interconnect metallization can be misaligned and the selected gates will be protected by its etch barrier and not be exposed to the opening. Further, local interconnect conductive material can pass over a gate or unrelated resistor without shorting the gate/resistor.

Forming local interconnects in integrated circuits

A method of forming field isolation in a semiconductor substrate, such as shallow oxide trenches, for isolation of FET transistors, including complementary FETs such as CMOS, with selected sections of said trenches extending above the substrate and being coplanar with the upper surface of subsequently formed polysilicon gates. An etch protective layer is used during the formation and the filling of the trench openings so that the top of the trenches are coplanar with upper surface of the etch protective layer. Selected sections of the trenches are masked and protected prior to planarization of the non-masked trenches to the bottom edge of the etch protective layer. After deposition and planarization of the poly, the upper surface of a deposited polysilicon layer for forming polysilicon gates of FET transistors is coplanar and self-aligned with the upwardly extending selected sections of the field isolation trenches.

Method for self-aligning polysilicon gates with field isolation and the

A static random access memory (SRAM) cell has a decreased cell size and utilizes transistors disposed in a number of trenches. Four trenches generally contain six transistors associated with the memory cell. The transistors are provided as sidewall transistors which are coupled to buried bit lines, VSS nodes, and VDD nodes at the bottom of the trenches. A first trench includes a driver transistor and a load transistor which have gates coupled together by a bridge over the trench. Another bridge is provided over the bridge over the trench to couple the source of the load transistor to the drain of the driver transistor. The drain of the driver transistor is coupled to another drain of the access gate transistor. The access gate transistor is located in a trench with a access gate transistor from another cell. The buried bit line is located in the trench with the access gate transistors.

Static random access memory cell having buried sidewall transistors,

A method of forming minimal gaps or spaces in a polysilicon conductive lines pattern for increasing the density of integrated circuits by converting an area of the size of the desired gap or space in the polysilicon to silicon oxide, followed by removing the silicon oxide. The preferred method is to selectively ion implant oxygen into the polysilicon and annealing to convert the oxygen implanted polysilicon to silicon oxide. As an alternative method, an opening in an insulating layer overlying the conductive line is first formed by conventional optical lithography, followed by forming sidewalls in the opening to create a reduced opening and using the sidewalls as a mask to blanket implant oxygen through the reduced opening and into the exposed polysilicon conductive line. After annealing, the implanted polysilicon converted to silicon oxide and removed to form a gap or space in the polysilicon conductive line pattern substantially equal in size to the reduced opening. Instead of blanket implanting with oxygen, thermal oxidation can be used to convert the exposed polysilicon to silicon oxide.

Growing community of inventors

Cupertino, CA, United States of America

Asim A Selcuk