Xilinx, Inc.

Other

Catalyst Semiconductor, Inc.

Integrated Silicon Solution Incorporated

Nexcom Technology, Inc.

Asim A Bajwa

Ping-Chen Liu

Christophe J Chevallier

David K Wong

Amitava Majumdar

Richard William Swanson

Robin John Jigour

Jongheon Jeong

Darrell D Rinerson

Steve K Hsia

Michel E Gannage

Anna W Wong

Suraj Ethirajan

Michael E Gannage

In an apparatus relating generally to an IC die, the IC die has a regulated power supply, a power supply grid, and a test circuit. The regulated power supply is biased between a source supply node and a source ground node, which are externally accessible nodes of the IC die. An internal supply node of the power supply grid is coupled to the regulated power supply. The test circuit is coupled to the internal supply node of the power supply grid. The test circuit is configured to test for at least one short in the power supply grid. The test circuit is configured to limit power through the power supply grid to less than that of a probe tip tolerance. The test circuit is configured to test for the at least one short in presence of background current leakage of the power supply grid.

Testing for shorts between internal nodes of a power distribution grid

A JTAG-programmable IC includes a memory array having redundant columns, a partial-width data register, and a full-width bitline register. A programming bitstream is shifted into the data register in discrete portions, with each portion being loaded into the bitline latch before the next portion is shifted into the data register. The programming bitstream portions fill the bitline latch sequentially unless a count indicator for a particular portion matches a predetermined defective column value, in which case that bitstream portion is rerouted to a region of the bitline latch associated with the redundant columns of the memory array. The count indicator is incremented with each new bitstream portion shifted into the data register. Once the programming bitstream is fully loaded into the bitline latch, the data is programmed into a selected row of the memory array in page mode.

Column redundancy scheme for non-volatile flash memory using JTAG input protocol

A resistive divider for a voltage multiplier circuit minimizes output voltage overshoot by capacitively coupling the tap point of the resistive divider to the output terminal of the voltage multiplier circuit via the parasitic capacitance of the resistive divider. For a resistive divider that includes a resistive structure formed over a dielectric layer formed on a doped well, this capacitive coupling can be performed by connecting the well to the output terminal of the voltage multiplier circuit. This capacitive coupling improves the response time of the resistive divider, so that a scaled test voltage read from the tap point varies more rapidly than the elevated output voltage of the voltage multiplier circuit. Therefore, the scaled test voltage provides charging control that increases the elevated output voltage in gradual increments that prevent the elevated output voltage from exceeding a target output voltage.

High voltage regulation circuit to minimize voltage overshoot

A serially programmable integrated circuit (IC) includes a memory array and multiple data registers daisy-chained by bypass logic. Each of the data registers is associated with a primary column grouping or redundant column grouping in the memory array. If a data register is associated with a primary column grouping that includes a defective column, the bypass logic bypasses that data register and incorporates one of the data registers associated with a redundant column grouping into the serial programming path of the IC. Therefore, when a programming bitstream is shifted into this serial programming path, defective columns in the memory array are automatically bypassed during the subsequent programming operation. To read a word from the memory array, any data stored in the redundant columns is first read out, and then the data from the primary columns is read out, bypassing the previously identified defective column groupings.

Column redundancy scheme for serially programmable integrated circuits

A memory device (100) includes a user device information sector (122) in addition to normal sectors (124) of a memory array. The user device information sector includes a product identification field (240) and a restricted address list field (250), and optionally includes a customer identification number field (220) and a serial number field (230). The product identification field includes such information as the manufacturer ID, a part number ID, package/speed identification, temperature/voltage identification, and byte locations for special options. The device identification field is factory programmed using a high voltage enabling signal applied to a write control logic circuit (102) in the memory device in conjunction with a 'Device Information Sector Program' instruction is applied to the SPI command and control logic (110). The device information sector is read from the application using a 'Read Device Information' instruction. Inadvertent corruption of the device information sector is avoided since a high voltage typically is not available in the application, and the 'Device Information Sector Program' instruction is not in the application command set.

Method and apparatus for providing accessible device information in

A computer system includes a computing device such as a microcontroller and a memory device. The memory device is illustratively a serial device connected to the serial port of the microcontroller. The memory device includes a page latch load circuit which provides serial I/O to the microcontroller and transfers I/O bits in a predetermined order to/from the page latches. Page latches are connected over many bit lines to a memory cell array. The page latches not only supports programming and reading of sectors in the memory cell array, but also provides one or more of the following functions: directly accessible to the microcontroller as an SRAM scratch pad, directly loadable from the memory cell array to facilitate single byte 'read-modify-write' operations, and loadable during programming operations to support real time applications.

Non-volatile programmable memory having a buffering capability and

A computer system includes a computing device such as a microcontroller and a memory device. The memory device is illustrtively a serial device connected to the serail port of the microcontrollerThe memory device includes a page latch load circuit which provides serial I/O to the microcontroller and transfers I/O bits in a predetermined order to/from the page latches. Page latches are connected over many bit lines to a memory cell array. The page latches not only supports programming and reading of sectors in the memory cell array, but also provides one or more of the following functions: directly accessable to the microcontroller as an SRAM scratch pad, directly loadable from the memory cell array to facilitate single byte 'read-modify-write' operations, and loadable during programming operations to support real time applications.

Non-volatile programmable memory having an SRAM capability

A memory device is disclosed that employs hot electron injection for programming operations and Fowler-Nordheim tunneling for erase operations. The memory device requires only a single 5 volt power supply and does not require an external high voltage supply for program or erase operations. The memory device includes a charge pump section that internally generates the high voltage required for programming and erase operations. The same charge pump section is used for both program and erase power requirements.

Memory circuit with pumped voltage for erase and program operations

A charge pump circuit is disclosed that enables the conversion of a low voltage to a higher voltage while delivering a substantial amount of current. The charge pump circuit includes a plurality of diode-capacitor voltage multiplier pump units connected in parallel with respect to each other. The plurality of pump units are switched at different times during the pump frequency to minimize noise generation. In one embodiment, the charge pump circuit is capable of delivering 8 mA of current.

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San Jose, CA, United States of America

Asim A Bajwa