Advanced Micro Devices Corporation

Asif Q Khan

James O Mergard

A bus bridge mechanism is provided with an automatic delayed transaction enable mode. When the automatic delayed transaction enable mode is activated, a bus master making a read request is immediately signaled to retry the transaction, and the read request is treated by the bus bridge as a delayed read request to be completed asynchronously. The delayed read request, when completed, supplies data to the bus master on the next retry of the read request by the bus master following the completion of the delayed read request.

Automatic early PCI transaction retry

A processor-based system such as a microcontroller supports a non-concurrent mode in which a bus master requesting ownership of a peripheral bus is forced to acquire ownership of both the peripheral bus and a processor bus. The system includes a peripheral bus arbiter to detect a peripheral bus request for the peripheral bus by a bus master, to generate a processor bus request for the processor bus in response to detecting the peripheral bus request, and to grant the bus master ownership of the peripheral bus if the bus master is granted ownership of the processor bus. The peripheral bus arbiter maintains ownership of the processor bus by the bus master until the bus master releases ownership of the peripheral bus. Similarly, a bus master seeking ownership of the processor bus can be forced to acquire ownership of the peripheral bus. The non-concurrent mode can be applied to various multi-bus architectures. One advantage of the non-concurrent mode is improved debug capability.

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Asif Q Khan