Amazon Technologies, Inc.

Nextio Inc.

Emulex Design & Manufacturing Corporation

Agere Systems Inc.

Other

Asif Khan

Christopher Joseph Pettey

Nafea Bshara

Mark Bradley Davis

Robert Michael Johnson

Islam Mohamed Hatem Abdulfattah Mohamed Atta

Robert Haskell Utley

Annette Pagan

Richard E Pekkala

Kiran Kalkunte Seshadri

Erez Izenberg

Thomas A Volpe

Prateek Tandon

Kypros Constantinides

Islam Atta

Anthony Nicholas Liguori

Sundeep Amirineni

David B Kramer

Marc John Brooker

Norbert Paul Kusters

Marc Stephen Olson

Steven Scott Larson

Carlos Javier Cabral

David Allen Brown

David Sonnier

David James Borland

Stephen David Glaser

Rahul Gautam Patel

Robert A Corley

Stanislav Spassov

Jon Nalley

Stephen Rousset

Tom Saeger

Taylor Phebus

Richard Pekkala

The following description is directed to a logic repository service. In one example, a method of a logic repository service can include receiving a first request to generate configuration data for configurable hardware using a specification for application logic of the configurable hardware. The method can include generating the configuration data for the configurable hardware. The configuration data can include data for implementing the application logic. The method can include encrypting the configuration data to generate encrypted configuration data. The method can include signing the encrypted configuration data using a private key. The method can include transmitting the signed encrypted configuration data in response to the request.

Logic repository service using encrypted configuration data

The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a reconfigurable logic region. The reconfigurable logic region can include logic blocks that are configurable to implement application logic. The host logic can be used for encapsulating the reconfigurable logic region. The host logic can include a host interface for communicating with a processor. The host logic can include a management function accessible via the host interface. The management function can be adapted to cause the reconfigurable logic region to be configured with the application logic in response to an authorized request from the host interface. The host logic can include a data path function accessible via the host interface. The data path function can include a layer for formatting data transfers between the host interface and the application logic.

Configurable logic platform

The following description is directed to a logic repository service supporting adaptable host logic. In one example, a method of a logic repository service can include receiving a first request to generate configuration data for configurable hardware using a specification for application logic. The method can include selecting a particular host logic shell from a group of host logic shells. The particular host logic shell can be used to encapsulate the application logic when the configurable hardware is configured. Configuration data for the configurable hardware can be generated. The configuration data can include data for implementing the application logic and at least a portion of the particular host logic shell. The method can include receiving a second request to download the configuration data to a host server computer comprising the configurable hardware. The configuration data can be transmitted to the host server computer in response to the second request.

Logic repository service supporting adaptable host logic

To improve data throughput and data transfer rate, a contiguous block of host memory can be allocated for data transfers between the host system and an integrated circuit device such as a peripheral component. By using a contiguous block of memory that acts as a circular buffer, the memory address field of memory descriptors can be eliminated because the host system only need to inform the data movement engine of the length of each data transfer. The data movement engine can maintain pointers to keep track of the memory address in the host memory to read from and write to. After each data transfer, the relevant pointer can be incremented by a value corresponding to the length indicated in the memory descriptor for the transfer. As such, it is not necessary for the host system to provide the data movement engine with the memory address of each transfer.

DMA engine that generates an address-less memory descriptor that does not include a memory address for communicating with integrated circuit device

Disclosed are techniques regarding aspects of implementing client configurable logic within a computer system. The computer system can be a cloud infrastructure. The techniques can include associating signature information with the client configurable logic for various purposes.

Client configurable hardware logic and corresponding signature

Methods and apparatus are disclosed for securely erasing partitions of reconfigurable logic devices such as FPGAs in a multi-tenant server environment. In one example, a method of securely erasing an FPGA includes identifying one partition of previously-programmed resources in the FPGA, erasing the identified partition by storing new values in memory or storage elements of the identified partition, and storing new values in memory or storage elements of additional external resources electrically connected to the integrated circuit and associated with the identified partition. Thus, other partitions and subsequent users of the identified partition are prevented from accessing the securely erased data. A configuration circuit, accessible by a host computer via DMA, can be programmed into the FPGA reconfigurable logic for performing the disclosed erasing operations.

Controlling access to previously-stored logic in a reconfigurable logic device

In one example, an integrated circuit includes a first circuit, a second circuit, a third circuit, and a fourth circuit. The first circuit is configured to receive an input value and generate a first intermediate value based on a first probability density distribution associated with the input value. The second circuit comprises a set of multiplexer circuits configured to select, from a first set of candidate values and based on the first intermediate value, a first product of the first intermediate value and a weight value. The third circuit is configured to generate a second intermediate value based on a sum of the first product and a second product received from another circuit. The fourth circuit is configured to generate an output value based on the second intermediate value and a second probability density distribution associated with the second intermediate value.

Artificial neural network architecture based on lookup table

The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a plurality of reconfigurable logic regions. Each reconfigurable region can include hardware that is configurable to implement an application logic design. The host logic can be used for separately encapsulating each of the reconfigurable logic regions. The host logic can include a plurality of data path functions where each data path function can include a layer for formatting data transfers between a host interface and the application logic of a corresponding reconfigurable logic region. The host interface can be configured to apportion bandwidth of the data transfers generated by the application logic of the respective reconfigurable logic regions.

Configurable logic platform with multiple reconfigurable regions

Methods and apparatus are disclosed for programming reconfigurable logic devices such as FPGAs in a multi-tenant server environment. In one example, a computing host includes one or more processors configured to execute a supervisor process and two or more user processes and a single FPGA integrated circuit configured into a plurality of partitions. The partitions include a host logic partition that is accessible only to the supervisor process executing on the computing host, and two or more accelerator partitions. Each of the accelerator partitions is configured to include a virtual debug unit with a logic analyzer that collects logic signals generated by logic within the respective accelerator partition and sends debug data indicating values of the logic signals to one of the user processes. In some examples, the host logic partitions and/or the accelerator partitions can be independently reprogrammed of each other within their respective portions of the single FPGA.

Extracting debug information from FPGAs in multi-tenant environments

A multi-tenant environment is described with configurable hardware logic (e.g., a Field Programmable Gate Array (FPGA)) positioned on a host server computer. For communicating with the configurable hardware logic, an intermediate host integrated circuit (IC) is positioned between the configurable hardware logic and virtual machines executing on the host server computer. The host IC can include management functionality and mapping functionality to map requests between the configurable hardware logic and the virtual machines. Shared peripherals can be located either on the host IC or the configurable hardware logic. The host IC can apportion resources amongst the different configurable hardware logics to ensure that no one customer can over consume resources.

Intermediate host integrated circuit between virtual machine instance and customer programmable logic

Disclosed herein are techniques for preventing or minimizing completion timeout errors on a computer device. An apparatus include a processing logic circuit and a timeout logic. The timeout logic is configured to: generate a timeout event based on a transaction not completed by the processing logic circuit within a timeout period; determine a number of the timeout events generated during a monitoring period; and responsive to determining that the number equals to or exceeds a threshold, reduce the timeout period.

Adaptive timeout mechanism

Growing community of inventors

Cedar Park, TX, United States of America

Asif Khan