International Business Machines Corporation

Texas Instruments Corporation

Ashwini K Nanda

Maged M Michael

Douglas James Joseph

Krishnan Sugavanam

Jonathan H Shiell

James Randal Moulic

Bruce David D'Amora

Steven D Krueger

Thomas Basil Smith, Iii

Ian Chen

James O Bondi

Simonjit Dutta

A system and method for accelerating the execution of applications in computing environments. The method includes receiving a request for execution of a plug-in of a computing application and analyzing a network for accelerators for executing the plug-in. The method further includes identifying a designated accelerator residing on a device that is remote from the application and executing the plug-in with the designated accelerator.

Plug-in accelerator

A structure and method comprises a data structure representing a characteristic of an object in the virtual interactive environment. The device further comprises a client simulator to perform a first simulation of the characteristic of the object in the virtual interactive environment and a server simulator to perform a second simulation of the characteristic of the object in the virtual interactive environment. The device further comprises a synchronizer to synchronize the first and the second simulations.

System and apparatus for managing latency-sensitive interaction in virtual environments

A system including a south bridge, a first processor connected to the south bridge, and a second processor connected to the south bridge. The system further includes at least one device connected to the south bridge, and a resource manager coupled to the south bridge that allocates use of the at least one device between the first processor and the second processor.

South bridge system and method

A method and structure for an emulation system comprises of a plurality of field programmable gate arrays adapted to emulate nodes of a multi-node shared memory system, a plurality of cache directories, each connected to one of the arrays, and a plurality of global coherence directories, each connected to one of the arrays. Each of the global coherence directories maintain information on all memory lines remotely cached by each of the cache directories.

Real time emulation of coherence directories using global sparse directories

A system and method of maintaining consistent cached copies of memory in a multiprocessor system having a main memory, includes a memory directory having entries mapping the main memory, an access history information in the memory directory entries, and a directory cache having records corresponding to a subset of the memory directory entries. The memory directory may be a full map directory having entries mapping all of the main memory or a sparse directory having entries mapping to a subset of the main memory. The method includes the steps of receiving a signal indicating a processor cache miss, retrieving a memory directory entry from the memory directory, updating the access history of the memory directory entry, selecting a directory cache line based on its access history and allocating the directory cache line for replacement, and writing the memory directory entry into the directory cache.

State-based allocation and replacement for improved hit ratio in directory caches

A method and structure for a &ldquo;dynamic CCR/sparse directory implementation,&rdquo; includes maintaining state information of the main memory cached in the shared caches of the other compute nodes, organizing a cache directory so that the state information can be stored in a first area efficient CCR directory format, switching to a second sparse directory format if the entry is shared by more than one other compute node, and dynamically switching between formats so as to maximize the number of entries stored in the directory.

Method and system for organizing coherence directories in shared memory systems

A method and system for the parallel implementation of protocol engines based on memory partitioning. The method comprises the steps of partitioning a shared memory space into multiple mon-overlapping regions; and for each of the regions, using a respective one protocol engine to handle references to the region, independently of the other protocol engines. Preferably, the memory is partitioned into the non-overlapping regions either by using address interleaving or by using address range registers to identify address ranges for said regions. Also, preferably the protocol engines operate independent of each other and handle accesses to the memory regions in parallel.

Parallel implementation of protocol engines based on memory partitioning

A system and method for communicating messages between nodes of a packet switched communications network, with each message having a defined message type and including message content. The system includes one or more second level channel interface devices connected with a first node for tracking information relating to bi-directional communication of packets over a communications channel established between the first and second network nodes; a device for receiving packets associated with messages from the first node and generating message flits associated with the messages for communication over the channel based on message content associated with the received message packets; a device for receiving message flits associated with messages communicated from a second node and received via the channel and generating corresponding message packet content for storage at the first node; and, one or more first level channel interface devices associated with one or more second level channel interface devices and interfaced to a network switch device at each first and second node for communicating flits to and from a respective first and second node via the channel, wherein the communications channel established between the first and second network nodes includes a first and second level channel selected according to the message content.

Two level virtual channels

For a cache-coherent controller for a multiprocessor system sharing a cache memory, a split pending buffer having two components: a fully-associative part and an indexed part that can easily be made multi-ported. The associative part, PBA, include multiple entries having a valid bit and address fields, and the indexed part, PBC, includes entries including all the other status fields (i.e., the content part of the pending buffer entries). The split multi-ported pending buffer enables one request and one or more responses to be handled concurrently. Handling a request requires an associative lookup of PBA, a possible directory lookup, a possible read of PBC (in case of collision), and after processing the request in a request protocol handling unit, a possible PBA update, a possible PBC update, and a possible directory update, depending upon the cache coherence protocol implemented. Handling a response requires no PBA lookup, no directory lookup, a PBC read, and after processing the response in a response protocol handling unit, a possible PBA update, a possible PBC update, and a possible directory update, depending upon the cache coherence protocol implemented.

Split pending buffer with concurrent access of requests and responses to fully associative and indexed components

A method and structure for a system for maintaining coherence of cache lines in a shared memory multiplexor system comprises a system area network and a plurality of compute nodes connected to the system area network. Each of the computer nodes includes a local main memory, a local shared cache and a local coherence controller and computer nodes external to a given compute node include external shared caches and the coherence controller includes shadow directories, each corresponding to one of the external shared caches. Each of the shadow directories includes state information of the local main memory cached in the external shared caches. The shadow directories include only state information of the local main memory cached in the external shared caches.

Complete and concise remote (CCR) directory

A microprocessor (10) comprising a central processor unit core (12) operable to write information during a write cycle and a cache circuit (18) coupled to the central processor unit core and operable to evict information. The microprocessor further includes a combined storage queue (16) coupled to the central processor unit core and to the cache circuit. The combined storage queue includes a set of logical storage blocks (22c) which is operable to store both information written by the central processor unit core and information evicted by the cache circuit. Other circuits, systems, and methods are also disclosed and claimed.

Microprocessor circuits, systems, and methods using a combined writeback

A microprocessor-based system (2) is disclosed, based on an x86-architecture microprocessor (5). The system includes a memory address space (30) and a input/output address space (40), where input/output operations are performed in an I/O mapped manner. According to a first embodiment of the invention, burstable access is performed to areas of the main memory (32) which are blocked from cache access, by the microprocessor (5) asserting the cache request signal (CACHE#) in combination with the control signal (M/IO#) indicating that an I/O operation is requested. The memory controller (10) interprets this combination as a burst request to the non-cacheable memory location (32), indicates the grant of burst access by asserting the cache acknowledge control signal (KEN#), and the burst memory access is then effected. According to a second embodiment of the invention, burst access to non-cacheable memory space (32) is acknowledged by the memory controller (60) by way of a burst acknowledge signal (BEN#) that is separate from the cache acknowledgment signal (KEN#).

Microprocessor system with burstable, non-cacheable memory access support

A microprocessor comprising an instruction pipeline (36) comprising a plurality of successive instruction stages. An instruction passes from a beginning stage (38), through a plurality of intermediary stages (40 through 52), and to an ending stage (54) of the plurality of successive instruction stages. The microprocessor also comprises a storage circuit (58) coupled to receive program thread information output from a first stage (48) of the intermediary stages. Still further, the microprocessor comprises selection circuitry (56) comprising a first input, a second input, and an output for outputting output information from its first and second inputs. The first input of the selection circuitry is coupled to receive output information output from the first stage. The second input of the selection circuitry is coupled to receive program thread information output from the storage circuit. The output of the multiplexer is coupled to an input of a second stage (50) of the intermediary stages, wherein the second stage follows the first stage. Other circuits, systems, and methods are also disclosed and claimed.

Growing community of inventors

Mohegan Lake, NY, United States of America

Ashwini K Nanda