Globalfoundries Inc.

Ashwini Chandrashekar

Anbu Selvam Km Mahalingam

Somnath Ghosh

Ming He

Craig Child

Keith Donegan

Prakash Periasamy

Eswar Ramanathan

Colin Bombardier

Qanit Takmeel

Jeric Sarad

Embodiments of the disclosure provide a substrate structure for an integrated circuit (IC) structure, including: a first dielectric layer positioned above a semiconductor substrate; a first plurality of trenches extending at least partially into the first dielectric layer from an upper surface of the first dielectric layer; and a first metal formed within the first plurality of trenches, wherein a spatial arrangement of the first plurality of trenches causes coupling of surface plasmons in the first metal to at least one wavelength of an incident light.

Substrate structure with spatial arrangement configured for coupling of surface plasmons to incident light

Intermediate semiconductor devices and methods of reducing damage during back end of the line (BEOL) metallization and metal one (M1) layer integration scheme are provided. One method includes, for instance: obtaining a wafer having at least one contact region; depositing on the wafer a thin film stack having at least one layer of amorphous silicon (a-Si); performing lithography to pattern at least one opening; performing lithography to pattern at least one via opening and at least one trench opening; and removing the at least one a-Si layer. One intermediate semiconductor device includes, for instance: a wafer having at least one contact region; at least one first dielectric layer on the device; at least one second dielectric layer on the at least one first dielectric layer; and at least one a-Si layer on the at least one second dielectric layer.

Devices and methods of reducing damage during BEOL M1 integration

Growing community of inventors

Clifton Park, NY, United States of America

Ashwini Chandrashekar