International Business Machines Corporation

Ashwani K Malhotra

Roy Rongqing Yu

Eric D Perfecto

Kimberley A Kelly

John R Pennacchia

Wolfgang Sauter

David L Questad

Tien-Jen Cheng

Suryanarayana Kaja

Ajay Prabhakar Giri

Glen Nelson Biggs

Phillip W Palmatier

James Edward Fluegel

Charles F Carey

Bernt Julius Hansen

Donald M Brewer

Thomas Anthony Wassick

James Patrick Wood

Robert Paul Katz

Gregory S Boettcher

Ronald R Shields

A semiconductor chip for forming the same. The semiconductor chip includes M regular solder bump structures and N monitor solder bump structures, M and N being positive integers. If a flip chip process is performed for the semiconductor chip, then the N monitor solder bump structures are more sensitive to a cool-down stress than the M regular solder bump structures. The cool-down stress results from a cool-down step of the flip chip process. Each of the M regular solder bump structures is electrically connected to either a power supply or a device of the semiconductor chip. Each of the N monitor solder bump structures is not electrically connected to a power supply or a device of the semiconductor chip.

Semiconductor chip used in flip chip process

A semiconductor chip and methods for forming the same. The semiconductor chip includes M regular solder bump structures and N monitor solder bump structures, M and N being positive integers. If a flip chip process is performed for the semiconductor chip, then the N monitor solder bump structures are more sensitive to a cool-down stress than the M regular solder bump structures. The cool-down stress results from a cool-down step of the flip chip process. Each of the M regular solder bump structures is electrically connected to either a power supply or a device of the semiconductor chip. Each of the N monitor solder bump structures is not electrically connected to a power supply or a device of the semiconductor chip.

Monitoring cool-down stress in a flip chip process using monitor solder bump structures

A method for electroplating a film onto a substrate. Electrical power is supplied to the plating surface through electrical contact made to contact pads on the underside of the substrate. Contact to the contact pads is made within a liquid-tight region. The contact pads are connected to the plating surface through the substrate. Because the contact scheme is provided within a liquid-tight region on the underside of the substrate, the contacts do not erode or become plated, nor do they consume an area of the plating surface.

Method for electroplating a film onto a substrate

A process for producing a terminal metal pad structure electrically interconnecting a package and other components. More particularly, the invention encompasses a process for producing a plurality of corrosion-resistant terminal metal pads. Each pad includes a base pad containing copper which is encapsulated within a series of successively electroplated metal encapsulating films to produce a corrosion-resistant terminal metal pad.

Corrosion-resistant terminal metal pads for thin film packages

A semiconductor arrangement having a first active region and a dummy region on a surface of a substrate. The first active region and the dummy region are spaced from one another without any contact, and the dummy region is closer to an edge of the surface of the substrate in comparison to the first active region. Formed on the dummy region, first active region, and a portion of the substrate surface is a dielectric layer. The surface of the dielectric layer has an inactive portion and an active portion. A mask is disposed on the dielectric layer such that the mask contacts the inactive portion and does not contact the active portion.

Semiconductor arrangement preventing damage during contact processing

A process for fabricating and releasing a thin-film structure from a primary carrier for further processing. The thin-film structure is built on a metal interconnect disposed on a dielectric layer which, in turn, is deposited on a primary carrier. The thin-film structure and metal interconnect are released from the dielectric layer and primary carrier along a release interface defined between the metal interconnect and the dielectric film. Release is accomplished by disturbing the interface, either by laser ablation or dicing. The process of the present invention has at least three, specific applications: (1) the thin-film structure and metal interconnect can be released to yield a free-standing film; (2) the thin-film structure and metal interconnect can be laminated onto a permanent substrate (when building top-side down structures) and then released; and (3) the thin-film structure can be transferred to a secondary temporary carrier (when building top-side up structures) for further processing and testing, then transferred to a permanent substrate before releasing the thin-film structure and metal interconnect.

Process for transferring a thin-film structure to a substrate

Process for transferring a thin-film structure to a temporary carrier

Process for producing corrosion-resistant terminal metal pads for thin

A method and apparatus for electroplating a film onto a substrate. Electrical power is supplied to the plating surface through electrical contact made to contact pads on the underside of the substrate. Contact to the contact pads is made within a liquid-tight region. The contact pads are connected to the plating surface through the substrate. Because the contact scheme is provided within a liquid-tight region on the underside of the substrate, the contacts do not erode or become plated, nor do they consume an area of the plating surface.

Method and apparatus for making electrical contact to a substrate during

Process for releasing a thin-film structure from a substrate

A test pad is formed outside an array of pads included in connection structures such as pin mounting pads to which connection pins may be brazed in, for example, bottom side metallurgy of a multi-layer modular electronic package. In-line voltage plane testing may then be accomplished through temporary connections to the test pads for any desired layer, such as top side metallurgy distribution layers, while protecting the pin-mounting pads from physical and/or chemical damage or contamination during manufacturing processes for addition of layers to the electrical interconnection structure of the multi-layer module.

In-line voltage plane tests for multi-chip modules

Growing community of inventors

Newburgh, NY, United States of America

Ashwani K Malhotra