Synopsys, Inc.

Ashvin Mark Dsouza

Pei-Hsin Ho

Eduard Rudolf Cerny

Kevin Michael Harer

Manish Pandey

Per Mattias Bjesse

Himanshu Jain

Arunava Saha

A formal verification tool that verifies multiple sequentially-generated versions of a core circuit design by obtaining search path information from the formal verification solver for each property that is proven or disproven during a first formal verification session involving an earlier-generated circuit design version, and utilizing the search path information to perform search-path verification processes during a subsequent formal verification session to quickly verify the proven/disproven properties in a later-generated circuit design version. Each property's search path information includes counterexample traces or proof artifacts identifying the search operations utilized to achieve a corresponding counterexample or proof object that proves/disproves the property. Search-path verification involves applying the stored search path information to the later-generated circuit design version, and determining if the same counterexample or proof object is achieved. The stored search path information is also utilized to perform efficient path-influenced search processes when the search-path verification process fails.

Formal verification using cached search path information to verify previously proved/disproved properties

One embodiment provides a system, comprising methods and apparatuses, for simplifying a set of assumptions for a circuit design, and for verifying the circuit design by determining whether the circuit design satisfies a set of assertions when the simplified set of assumptions is satisfied. During operation, the system can simplify the set of assumptions by identifying, for an assertion in the set of assertions, a first subset of assumptions which, either directly or indirectly, shares logic with the assertion. Furthermore, the system can modify the first subset of assumptions to obtain a second subset of assumptions which either over-approximates or under-approximates the first subset of assumptions. Then, the system can refine the second subset of assumptions to either prove or falsify the assertion.

Automatic approximation of assumptions for formal property verification

One embodiment of the present invention provides a system that facilitates optimization and verification of a circuit design. The system can receive a set of assumptions associated with a circuit. The set of assumptions can specify a set of logical constraints on at least a set of primary inputs of the circuit. Note that the set of assumptions are expected to be satisfied during normal circuit operation. The system can generate a stimulus generator based in part on an assumption in the set of assumptions. The output values from the stimulus generator, which when assigned to the set of primary inputs of the circuit, cause the set of primary inputs to satisfy the assumption. Next, the system can generate a modified circuit by coupling the outputs of the stimulus generator with a set of primary inputs of the circuit. The system can then perform logic optimization on the modified circuit to obtain an optimized circuit.

Performing logic optimization and state-space reduction for hybrid verification

Relates to automatic conversion of assumption constraints, used in circuit design verification, that model an environment for testing a DUT/DUV, where the assumptions specify sequential behavior. Such assumptions are converted, with the use of logic synthesis tools, into a gate-level representation. For formal verification, a verification output is constructed from the gate-level representation and DUT/DUV assertion-monitoring circuitry. A formal verifier seeks to prove the verification output cannot indicate a design error. For simulation verification, the gate-level representation is converted into a hybrid representation comprising pipelines and combinational constraints. During simulation, the pipelines hold state information necessary for a solution, of the combinational constraints, to be in accord with the sequential assumption constraints. For certain sequential assumption constraints, the combinational constraints are insufficient to insure avoidance of deadend states. In a deadend state, an assumption is violated. A method is presented for augmenting the combinational constraints to avoid deadend states.

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Chelmsford, MA, United States of America

Ashvin Mark Dsouza