International Business Machines Corporation

Ashutosh Misra

Girish Gopala Kurup

Matthias Klein

Shridhar Narasimha Ambilkar

Bulent Abali

James J Bonanno

Narasimha R Adiga

Anthony Saporito

Peter H Hochschild

Deepankar Bhattacharjee

Mark S Farrell

Bruce C Giamei

Simon Weishaupt

Seetharam Gundu Rao

Jonathan D Bradbury

Anthony Thomas Sofia

Carl Alfred Bender

Timothy J Siegel

Pradeep Kumar Nalla

Raj Kumar Gajavelly

Marvin J Rich

Richard A Swetz

Niranjan Vaish

Suneel Pusarla

Suchismita Banerjee

Timothy John Slegel

Christian Jacobi

Brian Robert Prasky

Jason Raymond Baumgartner

Hubertus Franke

Adam B Collura

Damir Anthony Jamsek

Michael J Cadigan, Jr

Daniel Lipetz

Neal Richard Marion

Preetham M Lobo

Rahul Rao

Anil Shrikant Keste

Puja Sethia

Narendra Maganlal Desai

Raju B Pudota

Raju Bala Showry Pudota

Soumya Banerjee

Raju Bs Pudota

Narendra M Desai

Seetharam G Rao

Richard Swetz

Peter Heiner Hochschild

One or more units of decompressed data of a plurality of units of decompressed data is written to a target location for subsequent writing to memory. The plurality of units of decompressed data includes a plurality of symbol outputs and has associated therewith a plurality of decompression headers. A determination is made that the subsequent writing to memory of at least a portion of another unit of decompressed data to be written to the target location is to be stalled. A symbol start position of the other unit of decompressed data and a decompression header of a selected unit of the one or more units of decompressed data written to the target location are provided to a component of the computing environment. The decompression header is used for the subsequent writing of the other unit of decompressed data to memory.

Select decompression headers and symbol start indicators used in writing decompressed data

Compressing data includes hashing a first token length of an incoming data steam into a hash table, where the first token length includes a plurality of bytes. A second token length of the incoming data stream may be hashed into the hash table. The second token may be larger than the first token length and includes the plurality of bytes. The method may further include automatically comparing which token length enabled more efficient data compression, and automatically adjusting at least one of the first and second token lengths based on the comparison.

Automatic hash function selection

Various embodiments are provided for managing multiport banked memory arrays in a computing system by a processor. One or more conflicts may be eliminated in a multiport banked memory array upon receiving one or more write operations, read operations, or a combination thereof according to a selected priority and access protocol.

Minimizing conflicts in multiport banked memory arrays

Compression of data is facilitated by locating matches within the data to be compressed. A first technique is used to determine whether there is at least one matching string in the data to be compressed, and a second technique, different from the first technique, is used to determine whether there is at least one matching record in the data to be compressed. Based on there being at least one matching string in the data to be compressed, at least one indication of the at least one matching string is provided to an encoder to facilitate compression of the data. Further, based on there being at least one matching record in the data to be compressed, at least one indication of the at least one matching record is provided to the encoder to facilitate compression of the data. It is transparent to the encoder whether the first technique or the second technique is used to provide one or more matches.

Record-based matching in data compression

A system architecture is provided and includes an on-chip coherency unit, a processing unit, an accelerator and dedicated wiring. The processing unit is communicative with the on-chip coherency unit via a first interface. The accelerator is communicative with the on-chip coherency unit via a second interface. The accelerator is configured to be receptive of a request to execute lossless data compression or decompression from the processing unit and to responsively execute the lossless data compression or decompression faster than the processing unit. The processing unit and the accelerator are directly communicative by way of the dedicated wiring.

Instant quiescing of an accelerator

Embodiments of the invention are directed to a DEFLATE compression accelerator and to a method for verifying the correctness of the DEFLATE compression accelerator. The accelerator includes an input buffer and a Lempel-Ziv 77 (LZ77) compressor communicatively coupled to an output of the input buffer. A switch is communicatively coupled to the output of the input buffer and to the output of the LZ77 compressor. The switch is configured to bypass the LZ77 compressor during a compression test. The accelerator further includes a deflate Huffman encoder communicatively coupled to an output of the switch and an output buffer communicatively coupled to the deflate Huffman encoder. When the switch is not bypassed, the compressor can be modified to produce repeatable results.

Verifying the correctness of a deflate compression accelerator

Embodiments are directed to a method for optimizing performance of a microprocessor. The method includes monitoring the performance of the microprocessor in each of a plurality of performance modes. The method further includes choosing a performance mode based on the monitoring. Thereafter, using the performance mode for a predetermined amount of time. Each of the plurality of performance modes is a branch prediction mode.

Heuristic method to control fetching of metadata from a cache hierarchy

Various embodiments are provided for length-limited Huffman encoding in a data compression accelerator in a computing environment by a processor. Symbol counts of a plurality of symbols in compressed data may be normalized and manipulated according to a maximum code length limiting operation such that those of the plurality of symbols having a least frequent symbol count have a symbol count equal to a maximum code length of a Huffman tree.

Length-limited huffman encoding

Embodiments of the invention are directed to a DEFLATE compression accelerator and to a method for reducing a latch count required for symbol sorting when generating a dynamic Huffman table. The accelerator includes an input buffer and a Lempel-Ziv 77 (LZ77) compressor communicatively coupled to an output of the input buffer. The accelerator further includes a Huffman encoder communicatively coupled to the LZ77 compressor. The Huffman encoder includes a bit translator. The accelerator further includes an output buffer communicatively coupled to the Huffman encoder.

Reducing latch count to save hardware area for dynamic Huffman table generation

An aspect includes a system architecture that includes a processing unit, an accelerator, a main source buffer, a main target buffer, and a memory block. The main source buffer stores a first part of a source symbol received from an external source. The main target buffer stores an output symbol received from the accelerator. The memory block includes an overflow source buffer that stores the first part of the source symbol received from the main source buffer. The accelerator fetches the first part of the source symbol stored in the overflow source buffer and a second part of the source symbol stored in the main source buffer, and converts the first and second parts of the source symbol together into the output symbol. The second part of the source symbol includes a part of the source symbol not included in the first part of the source symbol.

Spilling temporary results for accommodation of memory boundaries

A system and method to manage a non-universal encoder and a universal encoder for compression of data include receiving the data. The data includes symbols. The method also includes subdividing the data into a first set of data blocks and a second set of data blocks and generating a non-universal encoder using the first set of data blocks. The non-universal encoder includes first codes. Each of the first codes corresponds to one of the symbols in the first set of data blocks only and at least one of the first codes includes fewer bits than the symbol corresponding to the at least one of the first codes. The method further includes compressing the second set of data blocks using at least the non-universal encoder.

Management of non-universal and universal encoders

A system, method and computer program product for maintaining an age and validity of entries in a structure associated with a processor is disclosed. An age tracking matrix is created for the structure. Each row of the age tracking matrix corresponds to an entry of the structure and each column of the age tracking matrix corresponds to an entry of the structure. When initiating an entry: a row corresponding to the entry is determined and a field in the determined row that is on a diagonal of the matrix is marked. For each other field in the determined row, the values that are in a diagonal field that is in a same column of the field are copied into the field. A relative age of the entries is determined by counting a number of marked fields in a column of the age tracking matrix.

Age management logic

Growing community of inventors

Bengaluru, India

Ashutosh Misra