Smart Iops, Inc.

Other

Smart Lops, Inc.

Smart Ipos, Inc.

Picogem Corporation

Ashutosh Das

Ashutosh Kumar Das

Manuel Antonio d'Abreu

Kirankumar Muralidharan

Sathishkumar Udayanarayanan

A solid-state storage device is provided that includes: a controller; non-volatile memory; a device interface; and a protocol-independent interface configured to couple to any one of a plurality of network adapters and communication ports so as to enable the controller to transmit data from the any one of the plurality of network adapters and communication ports. The controller is configured to receive data formatted according to a first protocol from an accessing device via the device interface. The protocol-independent interface includes a plurality of contacts coupled to the controller by a plurality of signal lines that enable data transmission from the controller to the protocol-independent interface. Each of the signal lines of the plurality of signal lines and each of the contacts of the plurality of contacts are configured to be enabled or disabled to form different channels through the protocol-independent interface to accommodate various target protocols.

Devices and systems having a protocol-independent interface supporting a plurality of data protocols, and methods related thereto

Devices, systems, and methods are provided that cause a controller to receive a first command to read or write first data from or to a first logical address; and determine a first mapped logical address that the first logical address is mapped to. A first plurality of logical addresses is mapped to the first mapped logical address and includes the first logical address. The controller reads a first data structure at the first mapped logical address. The first data structure includes a pointer to a first intermediate physical address. The controller reads a second data structure at the first intermediate physical address. The second data structure includes a plurality of pointers to target physical addresses. The plurality of pointers includes a pointer to a first target physical address for the first logical address. The controller reads or writes the first data from or to the first target physical address.

Devices, systems, and methods of logical-to-physical address mapping

Systems for managing thermal dissipation in multi-stacked memory dies, and methods and computer-readable storage media related thereto, are provided. The system includes memory dies including memory blocks to store data. A processing component is configured to maintain memory block states for the memory blocks. The memory block states include: an open memory block state allowing write operations, and a closed memory block state preventing write operations. The processing component is further configured to: receive a first write command to store first data, and compute first relative distances between open memory blocks in the open memory block state. The processing component is further configured to: select a set of open memory blocks for a first write operation based on the first relative distances so as to manage thermal dissipation, and initiate the first write operation on the first set of open memory blocks.

Systems and methods for managing thermal dissipation in multi-stacked dies

In certain aspects, one or more solid-state storage devices (SSDs) are provided that include a controller and non-volatile memory coupled to the controller. The non-volatile memory can include one or more portions configured as main memory or cache memory. When data stored in the main memory is written to the cache memory for processing, the data in the main memory is erased. In certain aspects, storage systems are provided that include one or more of such SSDs coupled to a host system. In certain aspects, methods are provided that include: receiving, by a first such SSD, a first command to write data to memory; determining that the data is stored in a main memory and is to be written to the cache memory for processing; writing the data to the cache memory; and erasing the data from the main memory.

Devices, systems, and methods for configuring a storage device with cache

In certain aspects, dynamic remapping of memory addresses is provided and includes initiating a remapping of a logical block from a 'mapped block' to a “remapped block.” Logical address locations for the logical block are mapped to physical address locations in the mapped block. The mapped and remapped blocks include non-volatile memory. A read command is received and determined to be for reading from a logical address location of the logical block, and the logical address location is determined to be mapped to a physical address location. Data is read from the physical address location of the mapped block. A write command is received and determined to be for writing data to the logical address location. Data is written to the physical address location of the remapped block. The read command is received after the initiation of the remapping and before the writing of the data to the remapped block.

Devices, systems, and methods for dynamically remapping memory addresses

In certain aspects, a data storage device is provided including a distributed controller configured to communicate with a main controller; and first and second memory devices of respective first and second non-volatile memory technologies. The first and second memory devices are coupled to the distributed controller configured to control access to the first and second memory devices. In certain aspects, a system is provided including a main controller; first and second distributed controllers coupled to the main controller; at least one first memory device coupled to the first distributed controller; and at least one second memory device coupled to the second distributed controller. The main controller is configured to control access to the first and second distributed controllers. The first and second distributed controllers are configured to control access to the respective at least one first and second memory devices that include at least two non-volatile memory technologies.

Devices, systems, and methods for storing data using distributed control

In some aspects, devices, systems, and methods are provided that relate to data deduplication performed in data storage devices, such as solid-state drives (SSD) or drives of any other type. In some aspects, devices, systems, and methods are provided that relate to hierarchical data deduplication at a local and system level, such as in a storage system built with one or more SSDs having built-in data deduplication functionality. The hierarchical data deduplication utilizes the IDs in the data storage devices to decide if the incoming data has to be stored or if a copy of the incoming data is already stored. In hierarchical data deduplication, no IDs (or signatures) are required to be stored at a system level. In some aspects, data steering is provided that enables data storing coordination in a system that consists of a set of data storage device (e.g., SSDs) having built-in data deduplication.

Devices, systems, and methods for reducing storage utilization with data deduplication

Devices, systems, and methods are provided for dynamically reconfiguring storage devices with applications in real-time to meet user needs, such as running different applications. The devices, systems, and methods relate to a storage device that includes memory for data storage and a controller for storing data in the memory. The controller includes a processor configured to receive an indication to reconfigure the controller with an application that is user-selected; receive the application; reconfigure the controller with the application such that the controller is enabled to run the application; receive an indication to run the application with a set of data as input; receive the set of data; run the application with the set of data as input; and generate resulting data from running the application with the set of data as input.

Devices, systems, and methods for reconfiguring storage devices with applications

A system includes a controller for controlling communication between a first device and a second device connected by way of a communication interface. The controller that is associated with the first device is configured to receive a communication request from a processor of the first device for communicating with the second device. Based on the communication request, the controller is further configured to retrieve a set of instructions from an instruction memory that is associated with the first device. Further, the controller is configured to control the communication interface at each cycle of a clock signal by executing each instruction thus controlling the communication between the first and second devices at each cycle of the clock signal.

Communication interface control system

A data packet distributor (DPD) includes a memory and a data packet transmission device (DPTD) connected to the memory. The DPTD receives a first data packet and identifies a destination queue for attempting transmission of the first data packet. The attempt for transmission is unsuccessful when a second data packet associated with the identified destination queue is present in the memory or the identified destination queue is unavailable for receiving the first data packet. The DPTD stores the first data packet in the memory when the attempt is unsuccessful. The DPTD re-attempts the transmission of the first data packet to the identified destination queue at end of a time interval. The re-attempt is successful when the second data packet is absent in the memory and the identified destination queue is available for receiving the first data packet.

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Cupertino, CA, United States of America

Ashutosh Kumar Das