Nxp B.v.

Nxp Usa, Inc.

Ashutosh Jain

Khoi Mai

Stefano Pietri

Michael Todd Berens

Michael A Stockinger

Ateet Omer

Yikun Mo

Dylan John Rosser

Jaideep Banerjee

An analog-to-digital converter (ADC) includes a digital-to-analog converter (DAC), a comparator coupled to an output of the DAC, a successive approximation register (SAR) logic unit coupled to an output of the comparator, and a programmable delay unit. The comparator includes a preamplifier having an input coupled to the output of the DAC and a latch having an input coupled to the output of the preamplifier and an output coupled to the input of the SAR logic unit. SAR logic unit generates a control signal, and programmable delay unit adjusts a delay between the control signal and a delayed control signal based on at least one parameter, such that comparator receives control signal and delayed control signal. In some implementations, the parameter is at least one of a frequency of a signal input to the DAC, a source impedance of a circuit driving the input signal, and a preamplifier power mode.

Successive approximation register analog-to-digital converter with programmable sampling noise cancellation

A transmission gate includes a first P-type transistor and a second P-type transistor coupled in series between a first signal node and an internal node. The transmission gate is enabled by turning on the first P-type transistor and the second P-type transistor to communicate signals between the first signal node and the internal node. The transmission gate is disabled by turning off the first P-type transistor and the second P-type transistor to stop communicating signals between the first signal node and the internal node. While the transmission gate is disabled, a third P-type transistor having a first current electrode coupled to a circuit node between the first and second P-type transistors and a control electrode coupled to the first signal node is used to track voltage of the first signal node and, in response to the tracking, control a voltage level at the circuit node to limit a gate-to-source voltage of the first P-type transistor.

Charge injection protection devices and methods for input/output interfaces

During a sampling phase, an analog front end circuit connects input of a first sampling capacitor to an analog input signal and input of a second sampling capacitor to a reference signal, and connects first and second hold capacitors to ground. During a partial tracking phase, input of the first sampling capacitor is connected to the reference voltage and the input of the second sampling capacitor is connected to the analog input signal. The first hold capacitor is connected to a first output of a gain amplifier and the second hold capacitor to a second output of the gain amplifier. Output of the first sampling capacitor is coupled to a first input of an amplifier and output of the second sampling capacitor is coupled to a second input of the amplifier.

Analog front-end circuit capable of use in a sensor system

In an integrated circuit, a first current source is coupled between a first supply voltage and a first node. An output stage includes a first current steering PMOS transistor coupled to the first node, a first current steering NMOS transistor including a first current electrode coupled to the first current steering PMOS transistor at a second node, a second current steering PMOS coupled to the first node, and a second current steering NMOS transistor including a first current electrode coupled to the second current steering PMOS transistor at a third node. Voltage at the second node is used to drive a gate of the second current steering PMOS transistor, and voltage at the third node is used to drive a gate of the first current steering PMOS transistor. First and second programmable slew rate pre-drivers provide outputs to the gates of the first and second current steering NMOS transistors, respectively.

Integrated circuit having a differential transmitter circuit

A circuit includes a high voltage (HV) transistor having a first current electrode, a second current electrode, and a control electrode coupled to receive a control signal. The HV transistor is configured and arranged to be non-conductive when the control signal is at a first state and conductive when the control signal is at a second state. A low voltage (LV) transistor is coupled to the first current electrode of the HV transistor. An HV pad is coupled to the second current electrode of the HV transistor. An operating voltage rating of the HV pad exceeds an operating voltage rating of the LV transistor. A secondary electrostatic discharge protection device is coupled between the second current electrode of the HV transistor and a voltage supply terminal.

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Austin, TX, United States of America

Ashutosh Jain