International Business Machines Corporation

Ashutosh Goyal

Brian William Curran

Michael Thomas Vaden

David Allan Webber

A summing circuit for an adder decodes control signals to determine that the result should be manipulated, and generates a half-sum output which is used to produce a manipulated result based on the control signals. The half-sum output is combined with a previous carry bit to complete the sum operation. The control signals can invert the adder result, or force the result to be all 1's. These functions can be effectuated in a 3-way multiplexer that combines the operand inputs and control signals. For inversion, two separate logic circuits produce true and complement half-sums in parallel, and the appropriate half-sum is selected for the half-sum output. For a result of all 1's, a force_1 control signal pulls the half-sum output node to electrical ground and the final output is manipulated by gating the carry signals with the force_1 signal. The two functions are implemented without introducing additional delay.

Method of forcing 1's and inverting sum in an adder without incurring timing delay

A method of operating an arithmetic logic unit (ALU) by inverting a result of an operation to be executed during a current cycle in response to control signals from instruction decode logic which indicate that a later operation will require a complement of the result, wherein the result is inverted during the current cycle. The later operation may be a subtraction operation that immediately follows the first operation. The later instruction is decoded prior to the current cycle to control the inversion in the ALU. The ALU includes an adder, a rotator, and a data manipulation unit which invert the result during the current cycle in response to an invert control signal. The second operation subtracts the result during a subsequent cycle in which a carry control signal to the adder is enabled, and the rotator and the data manipulation unit are disabled. The ALU may be used in an execution unit of a microprocessor, such as a fixed-point unit.

Inverting data on result bus to prepare for instruction in the next cycle for high frequency execution units

A summing circuit for an adder decodes control signals to determine that the result should be manipulated, and generates a half-sum output which is used to produce a manipulated result based on the control signals. The half-sum output is combined with a previous carry bit to complete the sum operation. The control signals can invert the adder result, or force the result to be all 1's. These functions can be effectuated in a 3-way multiplexer that combines the operand inputs and control signals. For inversion, two separate logic circuits produce true and complement half-sums in parallel, and the appropriate half-sum is selected for the half-sum output. For a result of all 1's, a forcecontrol signal pulls the half-sum output node to electrical ground and the final output is manipulated by gating the carry signals with the forcesignal. The two functions are implemented without introducing additional delay.

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Austin, TX, United States of America

Ashutosh Goyal