Intel Corporation

Ashutosh Ashutosh

Adrien Lavoie

Oleg Golonzka

Cory E Weber

Aaron A Budrevich

Hemant V Deshpande

Ajay K Sharma

Huicheng Chang

Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a source/drain region in an NMOS portion of a substrate, wherein the source/drain region of the NMOS portion comprises at least one dislocation, and wherein a PMOS source/drain region in a PMOS portion of the substrate does not comprise a dislocation.

Methods of channel stress engineering and structures formed thereby

A method for improving the reliability of a high-k gate dielectric layer comprises incorporating a noble metal into a transistor gate stack that contains the high-k gate dielectric layer and annealing the transistor gate stack in a molecular hydrogen or deuterium containing atmosphere. The annealing process drives at least a portion of the molecular hydrogen or deuterium toward the high-k gate dielectric layer. When the molecular hydrogen or deuterium contacts the noble metal, it is converted into atomic hydrogen or deuterium that is able to treat the high-k gate dielectric layer and improve its reliability.

Reliability of high-K gate dielectric layers

A device is annealed in a deuterium atmosphere. Deuterium penetrates the device to a boundary, which is passivated by the deuterium.

Boundaries with elevated deuterium levels

Growing community of inventors

Hillsboro, OR, United States of America

Ashutosh Ashutosh