International Business Machines Corporation

Ashu Kohli

Nader Amini

Gregory N Santos

Daryl Carvis Cromer

James Anthony Pafumi

Alfredo Aldereguia

Cang Ngoc Tran

Richard Louis Horne

William Alan Wall

Jeffrey Allan Whaley

Thomas P Lanzoni

Kimberly Kibbe Sendlein

Christopher Edward Koob

A computer system has a graphics subsystem employing a rasterizer and a frame buffer, with a digital-to-analog converter for producing drive signals to a video display. A bus interface acts as a gateway between a PCI bus and the graphics subsystem; this interface manages commands and DMAs passing between the host processor and various parts of the graphics subsystem. Within the interface, two command FIFOs are employed, one for storing commands/data sent from the host for 2D display (window management) and another for 3D applications. Using two command FIFOs eliminates the need for host semaphore, FIFO draining, and the latency associated with these operations. Timers are provided in the interface, associated with the two command FIFOs, to manage and regulate the frequency with which the system automatically switches between 2D and 3D FIFO processing. Host intervention is minimized by use of a context macro store for holding locally the sequences for context save and context restore which are used repeatedly.

Computer graphics system with dual FIFO interface

A computer system is provided, comprising system memory and a memory controller which resides on a system bus for controlling access to the system memory, a bus interface unit and a direct memory access controller also residing on the system bus, and a central processing unit electrically connected with the memory controller which is able to read and write data to the system memory via the memory controller. The memory controller and the bus interface unit each operate, when either is in control of the system bus, at a clock frequency which is a multiple of the clock frequency at which the direct memory access controller operates on the system bus. The memory controller and the bus interface unit each operate, when the direct memory access controller is in control of the system bus, at the same clock frequency as that of the direct memory access controller. The clock frequencies of the memory controller, the bus interface unit and the direct memory access controller are each synchronized in time. The computer system thereby permits system bus devices, operating at different clock frequencies, to coexist on the system bus without hindering the performance of the faster speed devices.

Computer system with varied data transfer speeds between system

A method and system for improving bus-to-bus data transfers in a multi-bus computer system is provided. The system includes a system bus having a slave device attached thereto, a peripheral bus having a master device attached thereto, and a host bridge connecting the two buses. The system bus permits burst read transfers of data stored in the slave device, wherein a single address phase is followed by several data phases, but only if the first address corresponds to a prescribed system bus boundary. The peripheral bus is not subject to address boundary limitations, instead permitting burst read transfers beginning at any address. The host bridge includes logic for decoding a first address asserted by the master device to determine if it corresponds to a system bus boundary. If it does not, the logic commences a first read pre-fetch non-burst transfer of a first set of data stored in the slave device beginning at the first address and ending at a system bus boundary, and temporarily stores this first set of data in a buffer. The logic then commences a second read pre-fetch burst transfer of a second set of data stored in the slave device corresponding to data stored between system bus boundaries, and temporarily stores this second set of data in the buffer, so that both of the temporarily stored first and second sets of data may be read by the master device over the peripheral bus in a single burst read transfer.

Bus-to-bus read prefetch logic for improving information transfers in a

Hardware logic within a host bridge that connects a system bus to a peripheral bus using PCI bus architecture or a peripheral bus that uses a bus architecture similar to PCI. The hardware optimizes the speed at which data transfers are accomplished between the buses while translating the data transfers between the different architectures of the two buses.

Bus-to-bus pacing logic for improving information transfers in a

Bus-to-bus bridge for a multiple bus information handling system that

A device for generating back-to-back data transfers on a bus in an information handling system. A detector for determining whether a first address value and a second address are within a range, a first register connected to the detector for storing the first address until the device generates the second address, a second register connected to the detector for storing the range value, and a transfer state block for driving the second address on the peripheral bus without a turnaround cycle if the detector determines that the first and second addresses are within the range. Thus, back-to-back data transfers are provided.

Method and apparatus for providing back-to-back data transfers in an

Growing community of inventors

Delray Beach, FL, United States of America

Ashu Kohli