Intel Corporation

Ashraf H Wadaa

Shahrnaz Azizi

Zhongsheng Wang

Deepak Samuel Kirubakaran

Venkateshan Udhayan

Ajay Gupta

Chris Binns

Ahmed Shams

Sze Ling Yeap

Ariela Zeira

Efraim Rotem

Kristoffer Fleming

James G Hermerding, Ii

Russell Jerome Fenger

Chee Lim Nge

Ravikumar Balakrishnan

Jianfang Olena Zhu

Rajshree Chabukswar

Vasudev Bibikar

Nir Yizhak Balaban

Marc D Torrant

Leor Rom

Noor Mubeen

Michael Kishinevsky

Refael Mizrahi

Renji Thomas

Binu John

Patrick Kam-Shing Leung

Andrey Gabdulin

Lingjing Zeng

Sravan Akepati

Ryan Thompson

Georgina Saborio Dobles

Pietro Mercati

Trevor S Love

Nicholas Klein

A hardware and/or software (e.g., a controller and/or firmware or software) that monitors a remaining capacity of a battery and adjusts a continuum of system performance settings ranging from best performance to best energy efficiency. The controller starts with best performance setting (at the expense of energy efficiency), and then the controller gradually shifts toward energy efficiency setting (at the expense of performance) when a battery usage exceeds a pre-defined drain rate (e.g., there is a deficit in the battery remaining capacity until the next charge). The controller reverts from energy efficiency setting towards high performance setting when the battery drain rate or discharge rate slows down (e.g., there is a surplus in the battery remaining capacity until the next charge).

Predictable battery power management apparatus and method

A processor core energy-efficiency core ranking scheme akin to a favored core in a multi-core processor system. The favored core is the energy-efficient core that allows an SoC to use the core with the lowest Vfor energy-efficiency. Such Vvalues may be fused in appropriate registers or stored in NVM during HVM. An OS scheduler achieves optimal energy performance using the core ranking information to schedule certain applications on the core with lowest V. A bootstrap flow identifies a bootstrap processor core (BSP) as the most energy efficiency core of the SoC and assigns that core the lowest APIC ID value according to the lowest V. Upon reading the fuses or NVM, the microcode/BIOS calculates and ranks the cores. As such, microcode/BIOS calculates and ranks core APIC IDs based on efficiency around LFM frequencies. Based on the calculated and ranked cores, the microcode or BIOS transfers BSP ownership to the most efficiency core.

Energy-efficient core voltage selection apparatus and method

Methods, apparatus, systems, and articles of manufacture are disclosed that coordinate network traffic between a wireless network device and a computing platform. An example apparatus includes a wake-up selector to generate a target wait time parameter based on a workload type of a number of packets obtained from a network device and a user preference, the target wait time parameter indicative of a time interval that, when met, causes a modem to retrieve the number of packets, a data frame generator to generate a data frame that causes the network device to buffer the number of packets for the time interval, and a network packet controller to negotiate, using the data frame, the target wait time parameter with a network device.

Methods and apparatus for coordination of network traffic between wireless network devices and computing platforms

Methods, apparatus, systems, and articles of manufacture are disclosed. In one example, a compute device to manage energy usage and compute performance includes at least one memory, instructions, and processor circuitry. The processor circuitry executes the instructions to determine a system power mode based on first telemetry data associated with the compute device. The processor circuitry executes the instructions to provide user activity data and second telemetry data associated with the compute device to a classification system. The processor circuitry executes the instructions to configure a plurality of parameters to manage power consumption and performance of the compute device based on a classification by the classification system.

Methods and apparatus to manage energy usage and compute performance

In one embodiment, a processor includes: a plurality of cores to execute instructions; a power controller to control power consumption of the plurality of cores, the power controller to receive network traffic metadata from a classifier and control the power consumption of at least one of the plurality of cores based at least in part on the network traffic metadata; and a hardware feedback circuit coupled to the plurality of cores, the hardware feedback circuit to determine hardware feedback information comprising an energy efficiency capability and a performance capability of at least some of the plurality of cores based at least in part on the network traffic metadata. Other embodiments are described and claimed.

Using network traffic metadata to control a processor

An apparatus comprising: a model to generate adjusted tuning parameters of a thread scheduling policy based on a tradeoff indication value of a target system; and a workload monitor to: execute a workload based on the thread scheduling policy; obtain a performance score and a power score from the target system based on execution of the workload, the performance score and the power score corresponding to a tradeoff indication value; compare the tradeoff indication value to a criterion; and based on the comparison, initiate the model to re-adjust the adjusted tuning parameters.

Methods, systems, articles of manufacture, and apparatus to optimize thread scheduling

In one embodiment, a processor includes: at least one core to execute a workload; a voltage regulator to provide an operating voltage to the at least one core; and a power controller coupled to the voltage regulator. The power controller may control the voltage regulator to provide the operating voltage, and may have a voltage regulator control circuit to select one of a plurality of power state profiles based at least in part on a classification of the workload, and to cause an update to a power state of the voltage regulator according to the selected power state profile. Other embodiments are described and claimed.

System, apparatus and method for dynamic power state scaling of a voltage regulator for a processor

Growing community of inventors

Beaverton, OR, United States of America

Ashraf H Wadaa