Intel Corporation

Ashraf B Islam

Balaji Srinivasan

Yasir Mohsin Husain

Jaydip Bharatkumar Patel

Kevin E Arendt

Nicolas L Irizarry

Jonathan Y Wang

Techniques for current biasing for memory cells are disclosed. In the illustrative embodiment, a source follower sets a voltage on a bitline of a memory cell. The current through the source follower is limited by a current mirror in series with the source follower. When additional current is required that the source follower cannot supply, a feedback transistor is activated to provide additional current. Additionally, in some embodiments, the current through the feedback transistor is copied to a current mirror, and the copied current is used to sense the state of the memory cell.

Technologies for current biasing for three-dimensional crosspoint memory cells

A method, apparatus and system. The method includes: generating a feedback voltage Vin a feedback circuit coupled to one of a bitline node (BL) or a wordline node (WL) of each of a plurality of memory cells of a memory array, the feedback voltage to, in a thresholded state of said each of the memory cells, counteract a decrease in an absolute value of a voltage Vat said one of the BL or WL; generating, in a reference circuit, one of a reference voltage Vto track a feedback voltage of the feedback circuit or a mirror current Ito track a current Ithrough said each of the memory cells; and providing one of values for both Vand V, or for an output voltage Vcorresponding to I, to a sense circuitry, the sense circuitry to determine a logic state of said each of the memory cells based on a comparison of Vwith Vor based on V.

Apparatus, system and method to sense a logic state of a memory cell in a three-dimensional memory device

A method, apparatus and system. The method includes: generating, during a read operation of a memory cell, a mirror current iMir1 at one of a WL node or a BL node of the memory cell opposite, respectively, one of a BL side or a WL side of the memory cell to which a current mode sense circuitry is connected, the iMir1 to reduce a value of the read voltage from VDM1 to VDM2, wherein the read voltage is between the WL node and the BL node; and sensing, using the current mode sense circuitry, a logic state of the memory cell at VDM2.

Apparatus, system and method to reduce a read voltage across a memory cell and improve read sense margin

A variable reference based sensing scheme is described. In one example, performance of a memory command to access a crosspoint memory device such as a memory read or memory write command involves a sensing operation. In one example, a memory read operation involves applying a voltage across the memory cell and sensing current through the cell. The current through the memory cell is compared with one of multiple reference currents to determine the state of the memory cell. The reference current is selected based on the voltage applied across the memory for the sensing operation. Different reference currents may be used for different types of operations. For example, different reference currents may be selected for a write sensing operation than for a read sensing operation.

Variable reference based sensing scheme

A sensing circuit for sensing an analog signal includes a level shifter that shifts the analog signal from a high voltage domain to a low voltage domain. The signal originates from the high voltage domain, and is passed to the low voltage domain through the level shifter. A source line provides the analog signal, which can be selectively switched into a sense amplifier circuit. The sense amplifier is in the low voltage domain and generates a digital output to represent the sensed analog signal.

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El Dorado Hills, CA, United States of America

Ashraf B Islam