Synopsys, Inc.

Mentor Graphics Corporation

Ashok Vittal

Peter Ramyalal Suaris

Nagaraja Ravindranath Rao

Shiraj Robi Dutta

Ravi Rao

Pravin K Madhani

Robi Dutta

An efficient, gridless, cost-based coarse router having layer assignment for a computer controlled integrated circuit design. The coarse routing process is used during the wire routing phase of an integrated circuit design and fabrication process. During the coarse wire routing process, a number of obstructions are defined. Next, the horizontal and vertical passages between adjacent obstructions, through which wires may be routed, are determined. The costs for possible wire paths connecting a pair of pins are computed based upon wire density histograms associated with the various passages through which the paths traverse. The lowest cost path is then selected. In order to increase the processing speed, a pruning method is employed to minimize the number of possible paths to be considered. In some instances, there may be areas which are overly congested. For overly congested areas, a pseudo obstruction is artificially created by the coarse router. Thereby, it may be more cost effective to route a portion of the wire through multiple different metal layers. The histogram is then updated and the next wire is iteratively routed.

Interative, gridless, cost-based layer assignment coarse router for computer controlled IC design

An efficient iterative, gridless, cost-based router for a computer controlled integrated circuit design. The fine routing process is used during the wire routing phase of an integrated circuit design and fabrication process. During the wire routing process, wires are routed between pins of nets. The routing process of the present invention is gridless and utilizes lanes that are defined based on the boundaries of objects. The cost-based router computes a cost for each wire path, and the cost is based on: (1) the manhattan wire distance: (2) the layers in which the wire runs; and (3) any overlap the wire has with soft obstacles (e.g., other wires, etc.); and (4) an estimated cost to the target. Cost computation is reduced by considering only obstacles within the layer in which a lane is run. The number of paths determined for a wire route is reduced by pruning possible paths based on the placement of obstacles within the integrated circuit. Further pruning is performed by picking the lowest cost child lane in cases when several lanes select the same lane. Paths are also pruned by stopping along any path whose work-in-progress cost estimation exceeds the final cost of a path already discovered. In multi-pin nets, the routing process selects that path (of equal cost paths) between a source pin and a target pin that also runs closer to another unconnected pin of the multi-pin net. When a source-target wire route is performed for a multi-pin net, the unconnected pin is treated as the target and the source is considered as the source-target wire route.

Efficient iterative, gridless, cost-based fine router for computer controlled integrated circuit design

The present invention includes a net topology strategy, referred to as a J-tree model, that meets monotonicity and ring back constraints for nets with bi-directional drivers without much degradation in delay. The present invention includes a method that can be used to automatically construct a J-tree for a given net. A J-tree is generated by identifying at least two clusters of nodes and interconnecting the nodes so that each node has a sibling node that is the same distance from a parent node. Each cluster comprises at least a minimum geometric number of nodes. The nodes are interconnected by first locating a star point for each cluster so that the nodes in each cluster are equidistant from the star point. Then, the star point for each cluster is interconnected forming the topology.

Automatic topology synthesis and optimization

Growing community of inventors

San Jose, CA, United States of America

Ashok Vittal