Cswitch Corporation

Velogix, Inc.

Agate Logic, Inc.

Ashok Vittal

Hare Krishna Verma

Ravi S Sunkavalli

Sudip K Nag

Bo Hu

Chandra Mulpuri

Conrad Kong

A programmable logic structure is disclosed employing input logic routing cell (ILRC) multiplexers and output logic routing cell (OLRC) multiplexers for making local connections between dedicated logic cells. In a simple programmable logic structure, a dedicated logic cell (DLC) is implemented in a programmable logic structure comprising multiple ILRC multiplexers for port A and multiple OLRC multiplexers for port B. In a multi-level programmable logic structure, multiple columns of dedicated logic cells is designed with columns of dedicated local cells adjacent to each other where each DLC column is used to implement a particular logic function. In a first embodiment, local connections can be made between dedicated logic cells, e.g. an OLRC in a first DLC at level L making local point-to-point connections to an ILRC in a second DLC at level L+1. In a second embodiment, local connections can be made from any other dedicated logic cells, whether positioned horizontally or vertically relative to a relative point or multiplexer, and from any offset from a current logic and routing cell (LRC). In a third embodiment, local connections can be made by stitching a first OLRC to a second OLRC (for connecting to an ILRC), which allows lines from other columns or levels of DLC to reach an ILRC for a fast local interconnect.

Programmable logic cells with local connections

A function generator is described that can be configured as a combinational logic, sequential logic, or routing cell. The function generator couples to a plurality of selector blocks that select a wire from a plurality of inputs. The selected wires are inputs to a function generator. The function generator, when configured as a combinational logic cell, can generate any function of its inputs. The function generator, when configured as a sequential logic cell, behaves as a register, where any of the inputs can be directed to input data, clear, clock enable, or reset signals. The register is configurable to a falling or rising edge flip-flop or a positive or negative level sensitive latch. As a routing element, logic cells selects one of its inputs. The output of the programmable cell can fan out to one or more inputs of another integrated cell.

Programmable function generator and method operating as combinational, sequential and routing cells

Programmable function generator and method operating as combinational, sequential, and routing cells

A programmable logic device has a plurality of levels of programmable logic modules with fixed interconnections. The outputs of a level connect to inputs of the next level of programmable logic modules. The first level is fed from a bank of memory elements and the inputs to this bank of memory elements are derived from the last level. Crossbar switches are optionally inserted between a carefully chosen pairs of levels.

Programmable integrated circuit architecture

Growing community of inventors

Fremont, CA, United States of America

Ashok Vittal