Qualcomm Incorporated

University of California

Ashok Swaminathan

Nitz Saputra

Dongwon Seo

Shahin Mehdizad Taleie

Behnam Sedighi

Ian Galton

Andrew Weil

Christian Venerus

Negar Rashidi

Vinod Panikkath

Krishnaswamy Thiagarajan

Honghao Ji

Xilin Liu

Tonmoy Biswas

Siyu Yang

Gurkanwal Singh Sahota

Bhushan Shanti Asuri

Jong Hyeon Park

Sang-June Park

Chinmaya Mishra

Marzio Pedrali-Noy

Ibrahim Ramez Chamas

Bo Yang

Ayush Mittal

Haibo Fei

Sameer Vasantlal Vora

Zhilong Tang

Ping Wing Lai

Sumant Ramprasad

Jaswinder Singh

Sreenivasa Mallia

Eunyung Sung

Osama Elhadidy

Xinxin Yu

Peter Gazzerro

Sudharsan Kanagaraj

Yen-Wei Chang

Sy-Chyuan Hwu

Methods and apparatus for sharing digital-to-analog (DAC) converters in a reconfigurable DAC circuit to support two or more transmit chains of a wireless transmitter configured for different radio access technologies (RATs) and/or different transmitter architectures. One example DAC circuit generally includes at least four DACs and a plurality of switches coupled to outputs of the at least four DACs such that the DAC circuit is configured as a multi-channel DAC circuit with at least four channels for a first set of one or more frequency bands and as an interleaved DAC circuit with at least two channels for a second set of one or more frequency bands different from the first set of frequency bands.

Reconfigurable transmit digital-to-analog converter (DAC) circuit

Methods and apparatus for filtering a signal using a current-mode filter circuit implementing source degeneration. An example filter circuit generally includes an input node; an output node; a power supply node; a first transistor comprising a drain coupled to the input node; a second transistor comprising a drain coupled to the output node and comprising a gate coupled to a gate of the first transistor; a capacitive element coupled between the drain of the first transistor and the power supply node; a first resistive element coupled between the drain and the gate of the first transistor; a first source degeneration element coupled between a source of the first transistor and the power supply node; and a second source degeneration element coupled between a source of the second transistor and the power supply node.

Wideband current-mode low-pass filter circuits

Methods and apparatus for common-mode current removal in a digital-to-analog converter (DAC). An example DAC circuit generally includes a plurality of current-steering cells, a resistor ladder circuit coupled to the plurality of current-steering cells and having a plurality of shunt branches, and an adjustable resistance circuit coupled between middle nodes of the plurality of shunt branches and a reference potential node for the DAC circuit.

Common-mode current removal schemes for digital-to-analog converters

Methods and apparatus for adaptively adjusting a resistance of a resistor network in a digital-to-analog converter (DAC), such as a current-steering DAC for a transmit chain. An example DAC generally includes a plurality of DAC cells. One or more of the DAC cells generally includes a current source and a resistor network. The resistor network includes a plurality of resistive elements, has an adjustable resistance, and is coupled between a power supply rail and the current source. In this manner, the DAC may support a wide range of full-scale currents, while maintaining a higher degeneration voltage and reduced noise and mismatch for a given headroom. For certain aspects, the one or more of the DAC cells further include a plurality of switches (e.g., implemented with PFETs) coupled to one or more of the resistive elements and configured to adjust the resistance of the resistor network.

Resistor network with adaptive resistance for digital-to-analog converter (DAC)

In certain aspects, a method for providing a first drive clock signal and a second drive clock signal to a first sub-digital-to-analog converter (sub-DAC) and a second sub-DAC includes receiving an input clock signal, and dividing the input clock signal to generate a first divided clock signal and a second divided clock signal. The method also includes gating the input clock signal using the first divided clock signal to generate the first drive clock signal, and inputting the first drive clock signal to a clock input of the first sub-DAC. The method further includes gating the input clock signal using the second divided clock signal to generate the second drive clock signal, and inputting the second drive clock signal to a clock input of the second sub-DAC.

Clock driver for time-interleaved digital-to-analog converter

Certain aspects of the present disclosure provide a digital-to-analog converter (DAC) system. The DAC system generally includes a plurality of current steering cells, each comprising a current source coupled to at least two current steering switches, wherein control inputs of the at least two current steering switches are coupled to an input path of the DAC system. The DAC system may also include a current source toggle circuit configured to selectively disable the current source of at least one of the plurality of current steering cells, and a feedforward path coupled between the input path and at least one control input of the current source toggle circuit.

Digital amplitude tracking current steering digital-to-analog converter

Methods and apparatus for adaptively generating a reference voltage (V) for biasing a switch driver and corresponding switch in a digital-to-analog converter (DAC). The adaptive biasing scheme may be capable of tracking process, voltage, and temperature (PVT) of the DAC. An example DAC generally includes a plurality of DAC cells, each DAC cell comprising a current source, a switch coupled in series with the current source, and a switch driver coupled to a control input of the switch, the switch driver being configured to receive power from a first power supply rail referenced to a reference potential node; a regulation circuit comprising a first transistor coupled between the reference potential node for the DAC and the switch driver in at least one of the plurality of DAC cells; and a Vgeneration circuit coupled to the regulation circuit and configured to adaptively generate a Vfor the regulation circuit.

Adaptive switch biasing scheme for digital-to-analog converter (DAC) performance enhancement

Certain aspects of the present disclosure provide a digital-to-analog converter (DAC). The DAC generally includes a plurality of current-steering cells, each having a bypass switch, and a resistor ladder circuit having multiple segments. Each segment may include a first resistive element and a second resistive element, the bypass switch being configured to selectively provide a bypass current to a common node between the first resistive element and the second resistive element.

Digital-to-analog converter (DAC) with common-mode correction

Certain aspects of the present disclosure are directed to a circuit for switch control. The circuit generally includes a plurality of flip-flops, each of the plurality of flip-flops having an input coupled to a respective one of a plurality of enable signals, a NOR gate having inputs coupled to outputs of the plurality of flip-flops; a plurality of AND gates, each having an input coupled to a respective one of the plurality of enable signals and having another input coupled to an output of the NOR gate, and a delay element coupled between the output of the NOR gate and reset inputs of the plurality of flip-flops.

Techniques for generating switch control signals

A current digital-to-analog converter includes a binary current-generating section configured to generate a binary-weighted current based on a first set of control signals; a unary current-generating section configured to generate a unary-weighted current based on a second set of control signals; and a current combining circuit configured to add or subtract a reference current and a current generated by a current source of the unary current-generating section using the binary-weighted current.

Apparatus and method for measuring current source mismatches in current-steering DAC by re-using R2R network

An interleaved digital-to-analog converter (DAC) system may include a first sub-DAC and a second sub-DAC and may be configured to provide both a converter output signal and a calibration output signal. The converter output signal may be provided by adding the first sub-DAC output signal and the second sub-DAC output signal. The calibration output signal may be provided by subtracting one of the first and second sub-DAC output signals from the other. The calibration output signal may be used as feedback to adjust the phase of one of the sub-DACs relative to the other, to promote phase matching their output signals.

Image calibration for time-interleaved digital-to-analog converter

A communication circuit may include a first pair of digital-to-analog converters (DACs) coupled to an input of a first mixer and configured to generate first baseband signals. The communication circuit may further include a second pair of DACs coupled to an input of a second mixer and configured to generate second baseband signals. The second baseband signals may be shifted in phase relative to the first baseband signals.

Communication circuit including a transmitter

A method and apparatus for controlling a supply sensitivity of a ring oscillator stage are provided. The apparatus is configured to generate, via a voltage biasing module, a first bias signal for a PMOS biasing module based on a supply voltage and a second bias signal for a NMOS biasing module based on the supply voltage, bias, via the PMOS biasing module, triode PMOS degeneration of the inverting module based on the first bias signal, bias, via the NMOS biasing module, triode NMOS degeneration of the inverting module based on the second bias signal, receive an input via an inverting module, and output, via the inverting module, an inverted version of the received input based on the biased triode NMOS degeneration and the biased triode PMOS degeneration.

Ring oscillator architecture with controlled sensitivity to supply voltage

A droop detector includes: a plurality of input nodes, each input node configured to receive a supply voltage; an output node; a plurality of detector modules, each detector module comprises: an input terminal coupled to each input node, an output terminal coupled to the output node; and an input tracking unit configured as a voltage follower to detect a droop in the supply voltage coupled to each input node and output an output voltage that follows the supply voltage on the output terminal when the droop is detected on the supply voltage; and a comparator coupled to the output node and configured to output a control signal when the droop is detected.

Multi-input scalable rectifier droop detector

Methods, systems, and circuits for providing compensation for voltage variation are disclosed. A system includes: a voltage comparator configured to assert a control signal in response to detecting that one or more of power supply voltages droops below a threshold amount; a phase locked loop (PLL) configured to divide an output frequency for the PLL in response to the assertion of the control signal; a plurality of voltage sensors corresponding to the plurality of power supply voltages, the voltage sensors configured to output respective digital signals indicative of a voltage level of its corresponding power supply voltage; and a control circuit configured to control an oscillator frequency in the PLL during the open-loop mode responsive to the respective digital signals.

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Cardiff, CA, United States of America

Ashok Swaminathan