Lsi Logic Corporation

Suvolta, Inc.

National Semiconductor Corporation

Dsm Solutions, Inc.

Semi Solutions LLC

Fairchild Camera and Instrument Corp.

Semisolution Inc.

Other

Altera Corporation

Lsi Corporation

Gold Standard Simulations Ltd.

Photonic International Pte. Ltd.

Ashok K Kapoor

Michael D Rostoker

James S Koford

Ranko L Scepanovic

Alexander E Andreev

Stanislav V Aleshin

Edwin R Jones

Alexander S Podkolzin

Gobi R Padmanahben

Valeriy B Kudryavtsev

Madhukar B Vora

Nicholas F Pasch

Thomas R Wik

V Swamy Irrinki

Raymond T Leung

Alex Owens

Robert J Strain

Valeriv B Kudryavtsev

Reuven Avraham Marko

Samar K Saha

Ratan K Choudhury

Michael E Thomas

Christopher Luis Hamlin

Payman Zarkesh-Ha

Hua-Fang Wei

Azeez J Bhavnagarwala

Greg Burton

Nicholas K Eib

Damodar Reddy Thummalapally

Richard D Schinella

Keith K Chao

Hemraj K Hingarh

Asen Asenov

Thomas G Mallon

Prabhakar Pati Tripathi

Birendra Dutt

Gregory N Burton

Raj Rajasekharan

Gauri C Das

Lei Lin

J Frank Ciacchella

Satish Menon

Valerity B Kudryavtsev

Weiwei Song

Various embodiments of a micro-disc modulator as well as a silicon photonic device and an optoelectronic communication apparatus using the micro-disc modulator are described. In one aspect, a device includes a SOI substrate and a silicon photonic structure formed on a primary surface of the SOI substrate. The semiconductor substrate includes a silicon waveguide and a micro-disc modulator. The micro-disc modulator is adjacent to the silicon waveguide and has a top surface substantially parallel to the primary surface of the SOI substrate. The top surface of the micro-disc modulator includes one or more discontinuities therein. The micro-disc modulator may be a multi junction micro-disc modulator having two vertical p-n junctions with a single resonance frequency to achieve high-speed modulation and low-power consumption.

Micro-disc modulator, silicon photonic device and optoelectronic communication apparatus using the same

A MOSFET structure and method of manufacture that minimize threshold variations associated with statistical uncertainties of implanted source and drain extensions. The source and drain extensions are fabricated very late in the process using a material added to etched recesses immediately adjacent to the transistor's channel. In various embodiments, the added material may be germanium grown by selective epitaxy, doped silicon grown by selective epitaxy, or metallic materials created by deposition or by deposition and reaction.

Reduced variation MOSFET using a drain-extension-last process

In deep submicron memory arrays there is noted a relatively steady on current value and, therefore, threshold values of the transistors comprising the memory cell are reduced. This, in turn, results in an increase in the leakage current of the memory cell. With the use of an ever increasing number of memory cells leakage current must be controlled. Random access memories with a dynamic threshold voltage control scheme implemented with no more than minor changes to the existing MOS process technology is disclosed. The disclosed invention controls the threshold voltage of MOS transistors. Methods for enhancing the impact of the dynamic threshold control technology using this apparatus are also included. The invention is particularly useful for DRAM and NVM devices.

Dynamic random access memories with an increased stability of the MOS memory cells

In deep submicron memory arrays there is noted a relatively steady on current value and, therefore, threshold values of the transistors comprising the memory cell are reduced. This, in turn, results in an increase in the leakage current of the memory cell. With the use of an ever increasing number of memory cells leakage current must be controlled. Random access memories with a dynamic threshold voltage control scheme implemented with no more than minor changes to the existing MOS process technology is disclosed. The disclosed invention controls the threshold voltage of MOS transistors. Methods for enhancing the impact of the dynamic threshold control technology using this apparatus are also included. The invention is particularly useful for SRAM, DRAM and NVM devices.

Random access memories with an increased stability of the MOS memory cell

Variation resistant metal-oxide-semiconductor field effect transistors (MOSFET) are manufactured using a high-K, metal-gate 'channel-last' process. Between spacers formed over a well area having separate drain and source areas, a recess in the underlying is formed using a crystallographic etch to provide [111] boundaries adjacent the source and drain regions. An ion implant step localized by the cavity results in a localized increase in well-doping directly beneath the recess. Within the recess, an active region is formed using an un-doped or lightly doped epitaxial layer, deposited at a very low temperature. A high-K dielectric stack is formed over the lightly doped epitaxial layer, over which a metal gate is formed within the cavity boundaries.

Variation resistant MOSFETs with superior epitaxial properties

Use of a forward biased diode to reduce leakage current of transistors implemented on silicon on insulator (SOI) is a particular challenge due to the difficulty of achieving effective contact with the region beneath the gate of the transistor. An improved implementation in SOI gate fingers that reach under the source through tunnels that are contacted with a region outside the transistor. A further embodiment uses drain extension implants to provide good channel connection.

Apparatus and method for improved leakage current of silicon on insulator transistors using a forward biased diode

An apparatus and method of manufacture for metal-oxide semiconductor (MOS) transistors is disclosed. Devices in accordance with the invention are operable at voltages below 2V. The devices are area efficient, have improved drive strength, and have reduced leakage current. A dynamic threshold voltage control scheme comprised of a forward biased diode in parallel with a capacitor is used, implemented without changing the existing MOS technology process. This scheme controls the threshold voltage of each transistor. In the OFF state, the magnitude of the threshold voltage of the transistor increases, keeping the transistor leakage to a minimum. In the ON state, the magnitude of the threshold voltage decreases, resulting in increased drive strength. The invention is particularly useful in MOS technology for both bulk and silicon on insulator (SOI) CMOS. The use of reverse biasing of the well, in conjunction with the above construct to further decrease leakage in a MOS transistor, is also shown.

Method for reducing leakage current and increasing drive current in a metal-oxide semiconductor (MOS) transistor

A method for modeling a circuit includes generating a circuit model based on a netlist that defines a plurality of connections between a plurality of circuit elements. The circuit model includes a model of one or more of the circuit elements. The method further includes determining a wire width associated with at least a selected connection based, at least in part, on design rules associated with the netlist. Additionally, the method includes determining a wire thickness associated with the selected connection based, at least in part, on a signal delay associated with the wire thickness. Furthermore, the method also includes routing the selected connection in the circuit model using a wire having a width substantially equal to the wire width calculated for the connection and a thickness equal to the wire thickness calculated for the connection and storing the circuit model in an electronic storage media.

System and method for routing connections with improved interconnect thickness

Circuits using four terminal transistors are disclosed. Such circuits can include various static and dynamic logic circuits, flip-flops, multiplexer, tri-state driver, phase detector, logic having variable speeds of operation, and/or analog circuit with such four terminal transistors operating in a linear or nonlinear mode.

Circuit configurations having four terminal devices

A junction field effect transistor (JFET) can include a top gate structure and an active semiconductor region. The active semiconductor region can include a side surface and a top surface formed below the top gate structure. The active semiconductor region can also include a channel region formed below the top gate structure, a bottom gate region formed below the channel region, and a gate tie region formed on the side surface that makes an electrical connection between the top gate structure and the bottom gate region.

Junction field effect transistor (JFET) structure having top-to-bottom gate tie and method of manufacture

A semiconductor device that includes transmitter circuits and receiver circuits that share a common data line and method is disclosed. Each transmitter circuit may include a frequency modulator that receives a stream of data and provides a frequency modulated data output at a predetermined carrier frequency. Each receiver may include a band pass filter that allows a corresponding frequency modulated data output from a corresponding transmitter circuit to pass through to a demodulator while essentially excluding the other frequency modulated data. In this way, a plurality of transmitter circuits can simultaneously transmit data with each one of the plurality of transmitter circuits transmitting data to a predetermined receiver circuit.

Common data line signaling and method

This invention describes a method of building complementary logic circuits using junction field effect transistors in silicon. This invention is ideally suited for deep submicron dimensions, preferably below 65 nm. The basis of this invention is a complementary Junction Field Effect Transistor which is operated in the enhancement mode. The speed-power performance of the JFETs becomes comparable with the CMOS devices at sub-70 nanometer dimensions. However, the maximum power supply voltage for the JFETs is still limited to below the built-in potential (a diode drop). To satisfy certain applications which require interface to an external circuit driven to higher voltage levels, this invention includes the structures and methods to build CMOS devices on the same substrate as the JFET devices.

Integrated circuit using complementary junction field effect transistor and MOS transistor in silicon and silicon alloys

Metal-oxide semiconductor (MOS) transistors that are operable at voltages below 1.5V, that are area efficient, and that exhibit improved drive strength and leakage current that are disclosed. A dynamic threshold voltage control scheme is used that does not require a change to existing MOS technology processes. Threshold voltage of the transistor is controlled, such that in the Off state, the threshold voltage of the transistor is set high, keeping the transistor leakage to a small value. The advantages provided by apply to dynamic logic, as well as in the specific well separation imposed by design rules because well potential difference are lower than the supply voltage swing.

Method and apparatus for dynamic threshold voltage control of MOS transistors in dynamic logic circuits

Circuits using four terminal junction field effect transistors (JFETs) are disclosed. Such circuits can include various static and dynamic logic circuits, flip-flops, multiplexer, tri-state driver, phase detector, logic having variable speeds of operation, and/or analog circuit with such four terminal JFETs operating in a linear or nonlinear mode.

Circuit configurations having four terminal JFET devices

A junction field effect transistor comprises a silicon-on-insulator architecture. A front gate region and a back gate region are formed in a silicon region of the SOI architecture. The silicon region has a thin depth such that the back gate region has a thin depth, and whereby a depletion region associated with the back gate region recedes substantially up to an insulating layer of the SOI architecture.

Junction field effect transistor using a silicon on insulator architecture

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Palo Alto, CA, United States of America

Ashok K Kapoor