Motorola Corporation

Texas Instruments Corporation

Ashok H Someshwar

Bernard J Pappert

George L Brantingham

John K Eitrheim

Herchel A Vaughn

Jeffrey R Teza

Kenneth A Lies

Kirk N Holden

Ying-wai Ho

Warren S Graber

Peter L Harrod

An array multiplier calculates a Sticky-Bit concurrently with an iterative multiply operation using a predetermined number of multiplier arrays. An n-bit multiplicand operand provides a continuous input for each multiplier array. An n-bit multiplier operand is divided into a number of smaller sub-operands and each sub-operand is utilized for each cycle of the multiply operation. Each multiply cycle produces an intermediate accumulated partial product represented as sum and carry data, and a portion of the final product. The intermediate accumulated partial product is used as an input to a subsequent multiplier array for the following multiply cycle. A final accumulated partial product is summed in an adder to determine a completed product. During each cycle of the multiply operation, the Sticky-Bit detection logic detects and accumulates the Sticky-Bit concurrently with the multiply operation.

Concurrent sticky-bit detection and multiplication in a multiplier

A barrel shifter comprises a first plurality of bit lines, a second plurality of bit lines and a plurality of switchable interconnections therebetween. A first subset of the switchable interconnections provide each of a set of desired shifts, while a second subset of the switchable interconnections duplicate certain of the first subset thereof and shorten the worst-case path lengths through the shifter. The first and second pluralities of bit lines may comprise interleaved high- and low-order bit lines of two data buses. Interface means may provide the interleaving function and also may provide means for accomplishing at least one shift in addition to the set of desired shifts. Sense amplifiers may be included for sensing voltage transitions on each bit line.

Barrel shifter

A circuit for adding two N-bit binary numbers with an input carry bit, where N is an integer, by the carry select technique is provided. A ranked ordered plurality of section adders function in conjunction with rank ordered carry select logic circuits to initially provide two sum bits and two output carry bits for each bit position corresponding to carry input bits of zero and one, respectively. The section adders comprise full adders and are divided into at least two ranked groups in which sum bits are concurrently calculated in each group. Each full adder concurrently provides two sum bits for each rank ordered output sum bit. The rank ordered carry select logic circuits sequentially provide carry select bits which are used by the full adders to select one of the two sum bits as the output sum bit. Two output carry bits are concurrently provided by each group. One of the two output carry bits of the lowest ranked group is provided as a half carry output bit in response to the carry input bit. One of the two output carry bits of the highest ranked group is provided as the sum output carry bit in response to the half carry bit of the lower ranked group.

N-bit carry select adder circuit with double carry select generation

Improved access to programmable logic arrays is provided by continuously asserting and negating a latch inputs control signal, continuously asserting and negating a control signal which discharges a first logic section of the array to provide frequent, current inputs to a second logic section of the PLA and discharging the second section of the PLA only upon receipt of an access request. In the case of asynchronous access, it is also necessary to generate a synchronized data strobe from the unsynchronized one and to generate an acknowledge signal to indicate the presence of valid output data. The disclosed method and apparatus provide access which has a short access time and which also provides outputs which reflect relatively current states of the inputs thereto.

Method and apparatus for access to a PLA

A two stage synchronizer circuit for synchronizing an asynchronous input signal with a local clock signal includes a reference inverter for generating a reference signal, a first sense amplifier for amplifying the difference between the reference signal and the asynchronous input signal, buffer inverters coupled to the output on the sense amplifier, a second sense amplifier coupled to the output of the buffer inverters, and an output inverter for delivering the desired synchronized signal. The reference inverter and the first and second buffer inverters have the same switch point so as to substantially reduce the probability of the generation of a meta-stable output. Furthermore, the first and second sense amplifiers and output inverter also have the same switch point as the reference inverter.

Two state synchronizer

A memory for generating data signals responsive to a select signal, a means for generating an increment signal responsive to particular ones of the data signals, a counter for selectively outputting the select signal corresponding to a stored count value, and a means for selectively incrementing the stored count value in the counter responsive to the increment signal. In a preferred embodiment, the data processing system includes means for selectively generating first and second enable signals responsive to particular ones of the data signals and includes, a first counter for selectively generating a select signal corresponding to a stored count value responsive to the first enable signal and a second counter for selectively generating the select signal corresponding to a stored count value responsive to the second enable signal. The data processing system further includes a processing circuit for performing operations responsive to the data signals, input means for selectively outputting signals responsive to input stimuli, and output means for selectively providing an output representation responsive to an output representation signal.

Data processing system with multiple memories and program counter

A control state sequencer for controlling the execution of instructions of a microprocessor uses a PLA and a ROM to detect the current control state and instruction being processed by a processing unit and to provide the next control state of the instruction to the processing unit. An initial-state PLA and initial-state ROM detect when a new instruction is to be processed by the processing unit and provides the initial clock state of the new instruction to the processing unit.

Control state sequencer

A data processing system having a bus system for data communication employs a bus splitting circuit. This bus splitting circuit permits selective connection and isolation of individual buses of the bus system. A more flexible assortment of data communications paths among logic blocks coupled to the bus system is permitted by this arrangement in which some logic blocks may be coupled during one state of the bus splitting circuit and decoupled during the other state of the bus splitting circuit. By separating some of the buses via the bus splitting circuit, dual data transfers using the split buses is possible. In a preferred embodiment at least one of the logic blocks is a memory which is coupled to more than one of the buses, thus permitting simultaneous read and write operations, dual read operations or dual write operations.

Data processing system having multiple buses

A data processing system having a large slow main memory and having a small fast memory is disclosed with means for allowing slow memory calls to fast memory routines and means for allowing returns from programs executing in the fast memory so as to return to program execution in the slow main memory. Also disclosed is circuitry for selectively deactivating the main memory and for selectively activating the fast memory responsive to particular ones of data signals output from the main memory, and means for selectively deactivating the fast memory and for selectively deactivating the main memory responsive to predefined ones of data signals output from the fast memory, thereby allowing program calls embedded in the slow main memory to transfer execution control to the fast memory, and providing retransfer of execution control from the fast memory to the slow main memory in response to a RETURN code embedded in the fast memory. Thus, memory size and speeds may be selectively ratioed to obtain higher overall data processing system throughput.

Data processing system having interlinked slow and fast memory means

A memory mapped I/O scheme treats each I/O buffer as a memory element which can be addressed, written into or read from. Each I/O buffer has its own memory address decoder which eliminates the need for special select/control lines for each buffer and enables the use of a single address/data bus. Thus redesign and reconfiguration of the I/O buffers is more easily accomplished because it does not require new select/control lines to be laid out when buffer locations are changed.

Modular input/output system

In a microcomputer integrated circuit the option of selecting between an RC oscillator or a crystal oscillator for generating the clock for the microprocessor is made available. By making the selection during the manufacturing process, external pin outs and chip area are minimized.

Integrated circuit having elements for selectively forming an RC or a

A Binary Coded Decimal (BCD) incrementing circuit and memory. The incrementing circuit has a small amount of delay associated with it so that it may be utilized as a stage of a shift register memory. The incrementing circuit includes an adder circuit, a sampling circuit and a detector circuit. The sampling circuit samples the most significant bit of a BCD digit when the least significant bit of the same digit is being outputted from the memory. The adder circuit adds one to the least significant bit in response to a control signal or one to the other bits in response to a carry condition in the adder and to a decimal carry signal. The detector circuit is coupled to the output of the memory, to the sampling circuit and to the control signal for generating the decimal carry signal and disabling the adder circuit when the control signal is present and the BCD digit being outputted is a decimal nine.

Fast binary coded decimal incrementing circuit

A Read-Only-Memory (ROM) is addressed with a binary coded decimal (BCD) address in an address register or program counter. The ROM comprises an array of memory cells with associated row and column lines for addressing the array. Row and column decoders responsive to the address in the address register identify a unique row and column line for each BCD address. The row and column decoders comprise a plurality of decoders in cascaded levels. The decorders in any given level decode particular bits of the address in the address register; these decoders decode a one-out-of-a-prime-number, which prime number is a factor of the number of memory locations in the array.

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Austin, TX, United States of America

Ashok H Someshwar