Agere Systems Inc.

Lsi Corporation

Ashley Rebelo

Christopher J Wittensoldner

Gavin Appel

Donald Earl Hawk, Jr

Todd Snider

Allen S Lim

Ellis E Nease

Stephen M King

Jeffrey M Klemovage

Daniel L Gerlach

John J Krantz

Richard J Sergi

Multi-layer in integrated transmission line circuits are provided having improved signal loss characteristics. A multi-layer integrated transmission line circuit, such as a stripline circuit or a microstrip circuit, comprises at least one reference layer; at least one conducting layer having one or more conducting strips, wherein the at least one conducting layer is separated from the at least one reference layer by a substrate; and at least one additional layer positioned between the at least one conducting layer and the at least one reference layer. The multi-layer integrated transmission line circuit may also comprise a dielectric insulating material, such as an organic material or a ceramic material. The additional layers increase a dielectric thickness of the multi-layer integrated transmission line circuit to reduce dielectric losses.

Multi-layer integrated transmission line circuits having a metal routing layer that reduces dielectric losses

A method of generating a model of a leadframe IC package, a leadframe modeler and an IC design system are disclosed. In one embodiment the method includes: (1) adding connectivity information to a geometric representation of a leadframe, wherein the connectivity information represents electrical connections between the IC die and leads of the leadframe and (2) formatting the leads to represent BGA point of contacts for the IC die.

Method of generating a leadframe IC package model, a leadframe modeler and an IC design system

A method and article of manufacture for performing wire-bonding operations in an integrated circuit. In one aspect, the operations include the steps of bonding a wire to a first bond site in the integrated circuit and terminating the wire at a second bond site. The bonding and terminating steps are repeated for at least two differential wire bond pairs, and proximate differential wire bond pairs of the at least two differential wire bond pairs have substantially different wire bond profiles.

Method and article of manufacture for wire bonding with staggered differential wire bond pairs

An integrated circuit comprises an integrated circuit package and one or more circuit elements disposed within the integrated circuit package. The integrated circuit also comprises at least two differential wire bond pairs providing connections for at least one of the one or more circuit elements. Proximate differential wire bond pairs of the at least two differential wire bond pairs have substantially different wire bond profiles.

Integrated circuit with staggered differential wire bond pairs

An integrated circuit package having a multi-segment transmission line transformer for impedance matching a packaged integrated circuit, such as a driver or receiver, to a printed circuit board (PCB) transmission line to which the packaged chip is attached by, for example, solder balls. In one exemplary embodiment, a three-segment transmission line transformer provides improved broadband performance with the advantage of having a middle segment with a flexible length for easier routing. The length of each end segment of the three-segment transformer is adjusted to provide at least partial cancellation of reflections between the PCB and the transformer, and between the transformer and a circuit on the integrated circuit, respectively. Further, the inductive reactance of the solder balls and via wiring may be cancelled out by the transformed chip impedance to provide a non-inductive termination to the PCB transmission line at approximately one-half the highest data rate of the channel.

Integrated circuit package for high-speed signals

A wire bond circuit device has a circuit die in which substantially all of the input/output (I/O) pads are disposed along the outermost row of pads. A substrate onto which the die is disposed has wedges that are similarly arranged in rows, with the wedges used to carry I/O placed closest to the circuit die. As a result, lowest-tiered bond wire is used to connect the I/O-related pads to their respective wedges.

Growing community of inventors

Allentown, PA, United States of America

Ashley Rebelo