Xilinx, Inc.

Ashit Debnath

Dinesh D Gaitonde

Aashish Tripathi

Abhishek Kumar Jain

Maithilee Rajendra Kulkarni

A 3D device includes a first semiconductor chip and a second semiconductor chip stacked vertically. The first semiconductor chip includes a first plurality of tiles. The second semiconductor chip includes a second plurality of tiles. A bus electrically couples each of the first plurality of tiles to a corresponding one of the second plurality of tiles based on assignments of the first plurality of tiles and the second plurality of tiles to tile-to-tile pairs that define a minimized sum of bus delays among each possible tile-to-tile pairs. In each tile-to-tile pair, a net electrically couples each of a first plurality of pins to a corresponding one of a second plurality of pins based on assignments of the first plurality of pins to the second plurality of pins that define a minimized sum of net delays among each possible pin-to-pin pairs.

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Hyderabad Telangana, India

Ashit Debnath